Flash Memory Bad Block Management via Defect Map
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Solution Overview
Problem
Flash memory devices face inefficiencies due to defective blocks, which can lead to prolonged copy-back operations when managing bad blocks, impacting operational speed and reliability.
Innovation Solution
Incorporating a management block that directs memory access operations to reserved blocks for defective pages, eliminating the need for time-consuming copy-back operations by using a bad block management unit to replace defective page addresses with reserved block addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copy-back operation is used to manage bad blocks, then data can be preserved from defective blocks, but operational speed deteriorates due to prolonged duration
Solution Approach 1:
The patent applies preliminary action by pre-identifying and marking defective blocks before they are needed for data storage. The memory controller maintains a defect map that records bad block locations in advance, allowing the system to proactively redirect write operations to good blocks before defects occur, thereby eliminating the need for time-consuming copy-back operations and maintaining high operational speed while ensuring data preservation.
Solution Approach 2:
The patent introduces an intermediary defect map data structure that mediates between the memory controller and physical memory blocks. This defect map serves as a lookup table that translates logical addresses to physical addresses, allowing the system to indirectly access data without directly reading from defective blocks. The intermediary layer enables fast address translation while preserving data integrity, resolving the contradiction between reliability and speed.
2Reliability
If copy-back operation is performed to store valid data from bad blocks, then data integrity is maintained, but time consumption increases
Solution Approach 1:
The system performs preliminary identification of bad blocks and pre-allocates good blocks for data storage. By maintaining a defect map that records defective block locations in advance, the system can redirect write operations to valid blocks before data needs to be accessed, eliminating the need for time-consuming read-modify-write copy-back operations and significantly reducing time loss while maintaining data integrity.
Solution Approach 2:
The patent implements a virtual copying mechanism through the defect map, where logical addresses are copied to point to physical addresses in good blocks. Instead of physically copying data during read operations, the system maintains address mappings that effectively copy the logical-to-physical relationship, allowing fast address translation without actual data movement, thus preserving data integrity while minimizing time consumption.
3Reliability
If bad blocks are managed using traditional methods, then defective blocks can be identified, but operational efficiency deteriorates
Solution Approach 1:
The system performs preliminary identification of bad blocks during initialization or wear-leveling operations and stores this information in a defect map. This pre-processing allows the memory controller to quickly consult the defect map during normal operations and immediately redirect accesses away from defective blocks, maintaining high operational efficiency while ensuring reliable defect identification without requiring time-consuming checks during every read/write operation.
Solution Approach 2:
The memory controller implements self-service by autonomously managing the defect map and performing address translation without external intervention. The controller automatically detects bad blocks, updates the defect map, and redirects operations to good blocks based on the stored mappings. This self-managing capability maintains high operational efficiency by eliminating the need for host processor involvement in defect management while ensuring reliable identification and handling of defective blocks.
Data Source
AI summary
A memory system may include a plurality of non-volatile memory cells and a memory controller coupled to the plurality of non-volatile memory cells. The plurality of non-volatile memory cells may be arranged in blocks with each block including a plurality of pages of non-volatile memory cells. Moreover, the plurality of non-volatile memory cells may include a plurality of data blocks of non-volatile memory cells, a plurality of reserved blocks of non-volatile memory cells, and at least one management block of non-volatile memory cells. The memory controller may be configured to receive a data address for a page of non-volatile memory cells of a data block during a memory access operation, and to determine if the page of non-volatile memory cells corresponding to the data address is identified as being defective in the at least one management block. If the page of non-volatile memory cells corresponding to the data address is identified as being defective in the at least one management block, the memory controller may be further configured to direct the memory access operation to a page of a reserved block of non-volatile memory cells. Related methods are also discussed.