Flash Memory Segmentation for Bad Block Isolation
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Solution Overview
Problem
Flash memory chips often have bad blocks due to physical flaws, limiting their usable capacity and making them unsuitable for certain applications, as they cannot reliably save data, leading to inefficiencies in memory utilization.
Innovation Solution
Divide the flash memory into multiple logical areas of different capacities, including a bad-block area and additional logical areas for data storage, allowing for optimized memory space utilization by formatting and marking bad blocks, and enabling data loading and write-protection between these areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory chips are manufactured with high capacity, then storage capability is improved, but the presence of bad blocks reduces usable capacity and reliability
Solution Approach 1:
The flash memory chip is segmented into multiple independent logical memory areas (first logical area, second logical area, etc.), each with different capacities. This segmentation allows the system to isolate bad blocks within specific areas while maintaining functionality in other areas, thereby preserving overall reliability while utilizing total storage capacity.
Solution Approach 2:
The system dynamically changes the operational parameters by adjusting which logical areas are active based on bad block distribution. By formatting and marking bad blocks, the system modifies the usable capacity parameters of each logical area to optimize both storage utilization and data reliability.
2Productivity
If flash memory is divided into multiple logical areas with different capacities, then memory space utilization is optimized, but device complexity increases
Solution Approach 1:
The flash memory is divided into multiple logical areas (first logical area, second logical area, etc.) with different capacities, allowing optimized allocation of storage space based on specific application needs while maintaining a unified physical structure that manages complexity.
Solution Approach 2:
Each logical area can independently serve different functions or applications, allowing the same physical flash memory chip to provide multiple capacity options (e.g., 256MB, 512MB, 1GB) from a single device, enhancing versatility without requiring multiple separate chips.
3Reliability
If bad blocks are marked and isolated, then data reliability is improved, but usable storage capacity is reduced
Solution Approach 1:
Bad blocks are extracted and isolated into a dedicated bad-block area that is separated from the usable logical memory areas. This extraction ensures that unreliable blocks do not compromise data storage integrity while minimizing their impact on total usable capacity by confining them to a specific isolated region.
Solution Approach 2:
The system adjusts the capacity parameters of logical areas by dynamically allocating usable space around bad blocks. By formatting and marking bad blocks, the system modifies the effective capacity of each logical area to maximize usable storage while maintaining data reliability in good blocks.
Data Source
AI summary
A flash memory and a method for utilizing the same are disclosed. The method for utilizing a flash memory includes the steps of: a) providing a flash memory of a single chip; b) formatting the flash memory and marking bad blocks of the flash memory as a bad-block area free of reliably saved data; c) calculating a capacity of an available memory with the flash memory, wherein the available memory excludes the bad-block area of the flash memory; and d) dividing the available memory into a first storing memory and a second storing memory, wherein the first storing memory and the second storing memory have different capacities.