Flash Memory Bad Block Management via Repair Controller
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash memory devices face increased complexity and size due to the need for fuse or latch circuits in block decoders to manage bad blocks, which can lead to instability and errors in initial operations.
Innovation Solution
A flash memory device with a repair controller and disable circuit that generates block select signals to interrupt selection of bad blocks without using fuses or latches, allowing for a simpler row decoder structure and external indication of bad blocks to prevent access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fuse or latch circuits are added to block decoders to manage bad blocks, then bad block management capability is improved, but device complexity and chip size increase
Solution Approach 1:
The patent divides the bad block management function into two parts: (1) a simple block decoder without fuse/latch circuits that performs normal block selection, and (2) a separate repair controller that handles bad block detection and management. This segmentation removes the complexity from the critical block decoder path while isolating the management functionality to a dedicated controller module.
Solution Approach 2:
The repair controller acts as an intermediary between the block address input and the block decoder. It receives the block address, determines whether it corresponds to a bad block, and generates appropriate block select signals or interrupt signals. This intermediary approach allows the block decoder itself to remain simple while still achieving comprehensive bad block management through the coordinating repair controller.
2Reliability
If fuse or latch circuits are added to block decoders to manage bad blocks, then bad block management capability is improved, but manufacturing stability deteriorates due to fuse programming instability and latch errors
Solution Approach 1:
The patent extracts the unstable fuse and latch circuits from the block decoder structure. Instead of embedding these potentially unreliable components in the block decoder, the bad block management functionality is implemented through a repair controller using stable logic circuits and registers. This extraction eliminates the source of instability while preserving the essential bad block management capability.
Solution Approach 2:
The patent replaces the expensive and unstable fuse/latch mechanisms with simpler, more stable logic circuitry in the repair controller. The register-based implementation provides a more reliable and manufacturable solution that avoids the inherent instability of fuse programming and latch circuit operation during initial device operations.
3Productivity
If redundant memory cells and switching means are added to replace defective cells, then manufacturing yield is improved, but device complexity increases
Solution Approach 1:
The patent merges the bad block management functionality into the existing block decoder structure by adding a repair controller that works in conjunction with the normal block selection logic. Rather than creating separate redundant decoders or complex switching networks, the solution integrates repair capabilities into the existing decoder framework, achieving yield improvement without proportionally increasing complexity.
Data Source
AI summary
A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.