Flash Memory Bank Architecture for Concurrent Operations
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Solution Overview
Problem
NAND flash memory devices face inefficiencies in read, program, and erase operations due to long processing times and inability to perform other operations concurrently.
Innovation Solution
The flash memory device architecture is enhanced by dividing a bank into multiple independent banks within a semiconductor well, allowing simultaneous performance of read, program, or erase operations across different banks using shared I/O lines, page buffers, and voltage-switching mechanisms to manage distinct voltage levels for each operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single bank structure is used, then device complexity is reduced, but productivity deteriorates because only one operation can be performed at a time
Solution Approach 1:
The flash memory device is divided into multiple independent banks (first bank, second bank, third bank, fourth bank) that can operate simultaneously. Each bank has its own decoder and can perform read, program, or erase operations independently, allowing concurrent operations to improve productivity.
2Productivity
If multiple banks are introduced for concurrent operations, then productivity improves, but device complexity increases due to additional decoders and voltage switching mechanisms
Solution Approach 1:
Multiple banks share common resources including a single program/erase pump, common I/O lines, and a page buffer unit to reduce device complexity. The first and second switch units manage voltage distribution efficiently across banks, allowing concurrent operations without proportionally increasing overall system complexity.
Solution Approach 2:
The program/erase pump and page buffer unit serve multiple banks simultaneously, providing multi-functional capability. The switch units can route voltages to different banks as needed, allowing the same hardware components to support multiple operations across different banks.
3Ease of operation
If voltage switching mechanisms are added to manage multiple banks, then ease of operation improves for concurrent operations, but device complexity increases
Solution Approach 1:
The first and second switch units act as intermediaries between the program/erase pump and the multiple banks, managing voltage distribution efficiently. These switch units enable easy control of concurrent operations by routing voltages to appropriate banks without requiring complex direct control logic for each bank.
Data Source
AI summary
A flash memory device includes first to nth banks sharing an I/O line, a page buffer unit commonly connected to a bit line of the first to nth banks, for buffering data to be transmitted to the first to nth banks, a first X-decoder connected to a word line of the first banks, for applying a driving voltage to the word line of the first banks, a nth X-decoder connected to a word line of the nth banks, for applying a driving voltage to the word line of the nth banks, a program/erase pump for generating a program voltage/erase voltage applied to the first to nth banks, a first switch unit that switches the program voltage/erase voltage and transmits the voltage to the first banks and the first X-decoder, and a nth switch unit that switches the program voltage/erase voltage and transmits the voltage to the nth banks and the nth X-decoder.