Flash Memory Decoder Circuit With Selective Bit-Chunk Decoding

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Traditional low-density parity-check code decoding algorithms require excessive time for iterative decoding operations due to calculations being performed on all bits of a codeword, failing to meet the needs of existing products.

Innovation Solution

A decoder circuit and method that includes a channel value memory, variable node unit, barrel shifters, check node unit, decision unit, and strategy unit to selectively skip decoding calculations on bit chunks based on posterior probability values and conditions, reducing the number of iterative decoding operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional decoding algorithms perform calculations on all bits of a codeword in each iterative decoding operation, then decoding accuracy is maintained, but decoding time becomes excessively long

Engineering Contradiction:
Improvedecoding accuracyVSAvoiddecoding time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the codeword into multiple bit chunks and processes them separately. The channel value memory stores the codeword as multiple bit chunks, and the variable node unit processes specific bit chunks individually, allowing selective decoding of only necessary portions rather than processing all bits uniformly.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements partial action by performing decoding calculations on only specific bit chunks that require correction rather than all bits. The strategy unit determines which bit chunks need decoding based on posterior probability values, and the system skips decoding for bit chunks that already satisfy decoding conditions, thereby reducing overall decoding time while maintaining accuracy for error-prone portions.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If decoding calculations are performed on all bit chunks in every iterative operation, then complete error correction is achieved, but the average decoding time becomes too long

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces dynamic adaptability through the strategy unit, which adjusts the decoding process based on real-time assessment of posterior probability values. The system dynamically determines which bit chunks require decoding in each iterative operation, making the decoding process adaptive rather than static, thereby optimizing the balance between error correction and speed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements skipping by allowing the decoder to bypass bit chunks that already meet decoding conditions. The strategy unit identifies bit chunks with sufficient posterior probability values and skips their decoding in subsequent iterative operations, enabling the system to rush through already-correct portions and focus computational resources on problematic bit chunks.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Reliability

If the decoder processes every bit chunk in each iteration, then thorough decoding is ensured, but it cannot meet the timing requirements of existing products

Engineering Contradiction:
Improvedecoding thoroughnessVSAvoidtiming requirement compliance
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent performs preliminary assessment of bit chunks before full decoding processing. The variable node unit calculates posterior probability values for bit chunks in advance, and the strategy unit uses these pre-calculated values to determine which bit chunks require subsequent decoding. This preliminary action prevents unnecessary processing of already-correct bit chunks.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where the strategy unit continuously monitors posterior probability values and decoding conditions, adjusting the decoding process accordingly. The system uses feedback from previous iterative operations to inform subsequent processing decisions, ensuring that decoding thoroughness is maintained while adapting to timing constraints through intelligent resource allocation.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250284588A1Decoder circuit, flash memory controller, and decoding method
Publication Date: 2025.09.11 SILICON MOTION INC
  • US20250284588A1 patent drawing
  • US20250284588A1 patent drawing
  • US20250284588A1 patent drawing

AI summary

A decoding method includes: receiving and storing input data as a channel value in a channel value memory in a form of codeword; generating a posterior probability and a variable-to-check message according to a specific chunk of the channel value; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; using a check node unit to generate a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message; determining whether to flip at least one bit of the specific chunk according to the posterior probability; and, determining whether to ignore and skip execution of decoding calculation for the specific chunk in a next iterative decoding operation according to whether a decoding calculation result in a current iterative decoding operation matches with a specific condition.