Flash Memory ECC Using Multi-Threshold Bit Confidence Adjustment

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Solution Overview

Problem

The performance of SSD storage systems is significantly degraded due to exponentially increased read delays caused by frequent adjustments of read voltage thresholds in existing error correction methods, which are insufficient when bit errors exceed the error correction capability of ECC codes.

Innovation Solution

A method and apparatus that read data from a flash memory page using multiple voltage thresholds, determine and adjust confidence levels of data bits, and perform error correction decoding using these adjusted confidence levels to improve the success rate of error correction and reduce read delays, by jointly using data read at different voltage thresholds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Read Retry mechanism is used to adjust read voltage threshold multiple times to recover data, then data recovery capability is improved, but read delay increases exponentially from microseconds to milliseconds

Engineering Contradiction:
Improvedata recovery capabilityVSAvoidread delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary reading of the same page multiple times at different voltage thresholds before error correction decoding. By pre-acquiring multiple versions of the data with different confidence levels, the system avoids the need for repeated Read Retry attempts during actual data recovery, thus reducing the exponential read delay while maintaining data recovery capability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces soft information (confidence levels) as an intermediary between the raw read data and the error correction decoding process. This soft information guides the decoder to make more informed decisions about uncertain bits, improving data recovery success rate without requiring multiple expensive Read Retry operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If error correction decoding is performed on data read with default voltage threshold, then decoding speed is maintained, but decoding success rate decreases when bit errors exceed ECC capability

Engineering Contradiction:
Improvedecoding speedVSAvoiddecoding success rate
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent changes the parameter of voltage threshold during the reading process. By reading the same page multiple times at different voltage thresholds (e.g., default threshold, then adjusted thresholds), the system obtains multiple versions of the data with different confidence levels, thereby improving the probability of successful error correction decoding without significantly impacting overall decoding speed.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10691535B2Flash memory error correction method and apparatus
Publication Date: 2020.06.23 HUAWEI TECH CO LTD
  • US10691535B2 patent drawing
  • US10691535B2 patent drawing
  • US10691535B2 patent drawing

AI summary

A flash memory error correction method and apparatus is provided. The method includes determining a first data bit in a flash memory page, where the first data bit corresponds to different data respectively in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold and the data obtained by reading the flash memory page using the mth read voltage threshold; and then reducing a confidence level of the first data bit in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold; and performing, according to an adjusted confidence level of the first data bit, error correction decoding on the data obtained by reading the flash memory page using the (n+1)th read voltage threshold. Present disclosure effectively improves a success rate of error correction decoding, thereby significantly improving performance of an SSD storage system.