Flash Memory Logical Block Construction via Bit Error Rate Homogeneity
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Solution Overview
Problem
Existing memory systems using flash memory struggle with efficient data transfer and wear leveling due to variations in bit error rates among physical blocks, leading to uneven lifespan and reduced data storage capacity.
Innovation Solution
A memory system with a controller that constructs logical blocks by grouping physical blocks with similar bit error rates, using a bit-error-rate manager to calculate and manage bit error rates for each block, and employing wear leveling based on bit error rates to ensure balanced usage and extended lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If physical blocks are collected to construct logical blocks without considering bit error rates, then data transfer performance is improved through parallel operation, but wear distribution becomes uneven and reliability decreases
Solution Approach 1:
The patent applies local quality by constructing logical blocks from physical blocks with similar bit error rates, creating homogeneous groups. This ensures that each logical block has uniform wear characteristics, as physical blocks with comparable error rates exhibit similar degradation patterns and remaining lifespans, thereby resolving the contradiction between parallel data transfer and uniform wear distribution
Solution Approach 2:
The patent changes the parameter used for logical block construction from simple availability to bit error rate similarity. By calculating and comparing bit error rates of physical blocks, the system dynamically groups blocks with comparable reliability parameters into the same logical block, enabling both efficient parallel operations and balanced wear distribution across all logical blocks
2Quantity of substance
If physical blocks with different bit error rates are grouped together, then more physical blocks can be utilized, but the lifespan of logical blocks is reduced due to uneven wear
Solution Approach 1:
The patent maintains utilization of multiple physical blocks by creating homogeneous subgroups based on bit error rate similarity. Each logical block contains physical blocks with comparable reliability characteristics, ensuring that all blocks within a logical block wear down at similar rates, thereby maximizing the usable lifespan of each logical block while still utilizing a large number of physical blocks across multiple logical blocks
Solution Approach 2:
The patent segments the population of physical blocks into multiple logical blocks based on bit error rate ranges. This segmentation strategy divides physical blocks with similar reliability characteristics into separate logical blocks, preventing premature failure of any single logical block while maintaining high overall utilization of the physical block pool across the segmented logical blocks
3Device complexity
If wear leveling is not performed based on bit error rates, then system complexity is reduced, but data storage capacity is lost due to premature logical block failures
Solution Approach 1:
The patent introduces bit error rate as a key parameter for wear leveling management. By calculating and monitoring bit error rates of physical blocks and using this parameter to guide logical block construction and wear leveling operations, the system prevents premature failures and extends the overall data storage capacity without requiring overly complex management mechanisms
Solution Approach 2:
The patent implements feedback-based wear leveling by continuously monitoring bit error rates of physical blocks and using this information to make informed decisions about logical block construction and data placement. This feedback mechanism ensures that wear is distributed evenly across all logical blocks, maximizing the total writable data capacity while maintaining manageable system complexity
Data Source
AI summary
According to one embodiment, a memory system includes a bit-error-rate manager configured to manage information associated with a bit error rate for each physical block, a logical-block constructing unit configured to construct a logical block based on the information associated with the bit error rate, and a block manager configured to manage the correspondence between the logical block constructed by the logical-block constructing unit and the physical blocks. The logical block is a collection of a plurality of physical blocks.