Flash Memory Bit Line Voltage Biasing for Program Disturb Reduction
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Solution Overview
Problem
Flash memory devices experience program disturb effects due to charge leakage through drain select gates during programming operations, which can alter the programmed state of unselected memory cells, necessitating a need for alternate biasing schemes to mitigate these effects.
Innovation Solution
A biasing scheme that dynamically adjusts the bit line voltages from VINH_LOW to VINH_HIGH in response to specific threshold events during the programming process, reducing the potential difference across drain select gates and minimizing charge leakage, thereby reducing program disturb effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are biased to Vcc to inhibit programming, then programming of unselected cells is prevented, but charge leakage through drain select gates occurs causing program disturb effects
Solution Approach 1:
The patent applies dynamic biasing by transitioning bit lines from a first bias state (0V for programming) to a second bias state (Vcc for inhibition) based on real-time programming status. This dynamic adjustment optimizes both programming efficiency and program disturb prevention by adapting the bias state to the current operation phase.
Solution Approach 2:
The patent changes the voltage parameter of bit lines between two distinct states: 0V during programming and Vcc during inhibition. This parameter switching effectively controls the electrical characteristics of the bit lines to either enable or disable programming operations, resolving the contradiction between programming effectiveness and charge leakage prevention.
2Productivity
If bit lines are biased to 0V to enable programming, then programming speed is improved, but program disturb effects occur due to charge leakage
Solution Approach 1:
The system dynamically switches bit line biasing between 0V (for fast programming) and Vcc (for preventing charge leakage) based on whether cells are being programmed or inhibited. This ensures maximum programming speed when needed while preventing program disturb effects during inhibition phases.
Solution Approach 2:
The patent employs periodic switching of bit line bias states during the programming process, alternating between programming phases (0V bias for speed) and inhibition phases (Vcc bias to prevent leakage). This periodic action optimizes both productivity and reliability by timing the bias state changes with the programming operation cycles.
3Manufacturing precision
If alternate bit lines are enabled and inhibited sequentially, then programming coverage is improved, but programming time increases
Solution Approach 1:
The patent segments the bit line array into multiple groups that are independently controlled with different bias states. By dividing the bit lines into segments that can be simultaneously programmed or inhibited, the system achieves comprehensive programming coverage while reducing total programming time through parallel operations.
Solution Approach 2:
The patent applies partial programming action by enabling only specific bit lines (e.g., even or odd numbered lines) during each programming phase rather than all bit lines simultaneously. This selective approach maintains programming coverage while optimizing programming time by avoiding unnecessary operations on already-programmed or non-target cells.
Data Source
AI summary
Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage.