Flash Memory Bit Line Layout for Parasitic Capacitance Reduction
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Solution Overview
Problem
As flash memory designs become smaller and denser, parasitic capacitance between adjacent bit lines becomes more problematic, requiring improved circuit designs and layout techniques to reduce this capacitance.
Innovation Solution
The implementation of improved sensing circuit designs and bit line layouts that compensate for parasitic capacitance by strategically placing capacitors and switches to reduce the effect of adjacent bit lines' capacitance, and forming bit lines in different metal layers to increase distance and reduce resistance without increasing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If bit lines are placed in the same metal layer in close proximity to achieve compact layout, then area is reduced, but parasitic capacitance between adjacent bit lines increases
Solution Approach 1:
The patent applies dimensionality change by moving bit lines from the same metal layer to different metal layers. Specifically, first bit lines are formed in a first metal layer while second bit lines are formed in a second metal layer, physically separating them in the vertical dimension. This reduces parasitic capacitance between adjacent bit lines while maintaining compact horizontal layout, effectively resolving the contradiction between area reduction and parasitic capacitance reduction.
2Adaptability or versatility
If bit lines are lengthened to connect to more memory cells, then functionality is improved, but resistance and parasitic capacitance increase
Solution Approach 1:
The patent uses multiple metal layers to provide alternative routing paths. Bit lines can be extended in the horizontal dimension across different memory cell columns while utilizing the vertical separation between metal layers to minimize parasitic effects. This allows enhanced connectivity without proportionally increasing resistance and parasitic capacitance.
Solution Approach 2:
The bit line network is segmented into multiple independent bit lines across different metal layers. Each bit line can be optimized independently for its specific routing requirements, allowing selective extension where needed while maintaining shorter lengths elsewhere, thus balancing connectivity needs with signal integrity.
3Measurement precision
If sensing circuit complexity is increased to compensate for parasitic capacitance, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent converts the harmful parasitic capacitance into a beneficial effect by using it for differential sensing. The sensing circuit is designed to detect the voltage difference between bit lines, where the parasitic capacitance effects on each bit line tend to cancel out in differential mode. This allows accurate sensing without requiring complex compensation circuits.
Solution Approach 2:
The sensing circuit performs multiple functions: it senses memory cell data, compensates for parasitic capacitance effects, and provides differential signaling. By integrating these functions into a unified circuit architecture, the patent achieves high measurement precision without proportionally increasing device complexity.
Data Source
AI summary
Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.