Flash Memory Bit Line Leakage Reduction via Segmented Silicide
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Solution Overview
Problem
Conventional flash memory devices experience high leakage current between the semiconductor substrate and bit lines, leading to increased resistance and charge loss due to contamination of the trapping layer by organic matters during the polishing process.
Innovation Solution
A semiconductor device with a bit line and silicide layer where the silicide layer is not in contact with the semiconductor substrate, and sidewalls formed with silicon oxide films including phosphorus are used to reduce leakage current and prevent charge loss by getting contaminants in the trapping layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicide layers are formed in bit lines to reduce resistance, then the resistance of bit lines is lowered, but leakage current flows between the semiconductor substrate and bit lines via the silicide layers
Solution Approach 1:
The bit line structure is segmented into multiple regions: a first silicide layer within the bit line for conductivity, and a second silicide layer separated from the semiconductor substrate by an insulating film to prevent leakage. This segmentation allows each region to perform its specific function without causing harmful effects.
Solution Approach 2:
An insulating film is introduced as an intermediary layer between the second silicide layer and the semiconductor substrate. This intermediary prevents direct contact that would cause leakage current, while still allowing the silicide layer to provide conductivity in the bit line region.
2Reliability
If contact portions are provided for each bit line to reduce resistance, then the resistance is lowered, but the device area increases due to the large number of contact portions
Solution Approach 1:
Multiple contact portions are merged into a single continuous silicide layer that extends along the bit line. This combining of discrete contact portions into a unified structure reduces the overall device area while maintaining the low-resistance connection function.
Solution Approach 2:
The silicide layer serves multiple functions simultaneously: it provides low-resistance electrical connection like contact portions, and also extends continuously to prevent leakage current along the bit line length, replacing the need for multiple discrete contact structures.
3Ease of manufacture
If the trapping layer is exposed during polishing to flatten the surface, then the surface is flattened for subsequent processing, but organic matters from the polishing slurry contaminate the trapping layer causing charge loss
Solution Approach 1:
A protective film is formed over the trapping layer before the polishing process. This preliminary protective action prevents contamination during surface flattening, and the protective film is subsequently removed after polishing is complete, leaving the trapping layer clean and intact.
Solution Approach 2:
A protective film is introduced as an intermediary barrier between the polishing slurry and the trapping layer during the polishing process. This intermediary layer allows the surface to be flattened while preventing direct contact between contaminants and the sensitive trapping layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the resistance of the bit lines and minimizes charge loss by preventing current leakage and contaminant accumulation, enhancing the operational efficiency of flash memory devices.
Implementation Method 1
the sidewalls being formed with silicon oxide films including phosphorus... the silicon oxide films including phosphorus getter the contaminants in the trapping layer
Data Source
AI summary
A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus.