Flash Memory Bit Line Pre-Charging for Parasitic Capacitance Reduction
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Solution Overview
Problem
Flash memory devices face performance reduction and increased power consumption due to large parasitic capacitances in main bit lines, leading to longer reading operations and electromagnetic compatibility issues.
Innovation Solution
The solution involves maintaining the main bit line pre-charged to a constant voltage and discharging/pre-charging only the parasitic capacitances of selected local bit lines, using discharge selectors to bias local bit lines to a reference voltage during standby and enabling charge sharing for faster reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If main bit lines are discharged and pre-charged before each reading operation, then the reading operation can be performed, but the time required increases and power consumption peaks occur
Solution Approach 1:
The main bit lines are pre-charged to a suitable voltage level before the reading operation begins. This preliminary action ensures that when the reading operation starts, the main bit lines are already in the correct state, eliminating the need for time-consuming discharge and pre-charge cycles during the actual read operation.
Solution Approach 2:
The bit line hierarchy is segmented into main bit lines and local bit lines, with different pre-charging strategies applied to each. Main bit lines are pre-charged once and maintained at the suitable voltage level, while local bit lines are discharged and pre-charged as needed for specific reading operations. This segmentation allows the system to avoid repeatedly charging large capacitances.
2Productivity
If main bit lines are discharged and pre-charged in parallel, then reading operations can proceed, but power consumption peaks increase and electromagnetic emissions rise
Solution Approach 1:
Main bit lines are pre-charged to the suitable voltage level before the reading operation. This preliminary charging action distributes the power consumption over time, avoiding sudden peaks during the reading operation itself.
Solution Approach 2:
The pre-charging of main bit lines is performed periodically before reading operations rather than continuously or simultaneously with multiple read operations. This periodic action spreads the energy consumption over time, reducing peak power demands and associated electromagnetic emissions.
3Quantity of substance
If main bit lines are made longer and wider to increase storage capacity, then storage capacity improves, but parasitic capacitance increases
Solution Approach 1:
The bit line structure is segmented into a hierarchical system with main bit lines and local bit lines. This segmentation allows the main bit lines to be optimized for storage capacity while local bit lines handle the actual memory cell connections, reducing the overall parasitic capacitance impact.
Solution Approach 2:
Different parts of the bit line structure have different properties: main bit lines are designed with specific dimensions for optimal storage capacity, while local bit lines are designed with minimal dimensions to reduce parasitic capacitance. Each segment is optimized for its specific function rather than using uniform dimensions throughout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the duration of discharge, pre-charge, and equalization intervals, resulting in faster reading operations, lower power consumption, and improved electromagnetic compatibility.
Implementation Method 1
the parasitic capacitances of the local bit lines and of the main bit lines are typically discharged to the ground voltage
Implementation Method 2
then pre-charged to a suitable voltage level before each reading operation
Implementation Method 3
The capacitive coupling between the source line that is discharged and the local bit line causes a small change in voltage on the local bit line that is quickly attenuated by the sense amplifier
Data Source
AI summary
An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line. Each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal, for receiving a reference voltage, by a corresponding discharge selector. Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing circuitry to bias each main bit line to a pre-charge voltage during operation, and reading circuitry to select and access a group of memory cells during reading operations.