Flash Memory Bit Line Sensing Method for Read Time Reduction
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Solution Overview
Problem
The read throughput in 3-D memory structures is reduced due to the need to shield adjacent bit line coupling effects, leading to longer read times in odd-even architectures where only one set of bit lines is accessed during each read operation.
Innovation Solution
A sensing method that pre-charges both even and odd bit lines to a pre-charge level during reading, allowing the voltage of one set to be maintained while the other is discharged to ground, thereby reducing capacitive coupling and improving read time by shortening pre-charge time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate sensing between even and odd bit lines is used to avoid bit line coupling noise, then sensing reliability is improved, but read time is significantly increased
Solution Approach 1:
The patent applies preliminary action by pre-charging both even and odd bit lines to the same voltage level before sensing operations begin. This pre-charge preparation eliminates the need for sequential pre-charging during separate sensing, allowing faster transition to sensing mode while maintaining the reliability benefits of separate even/odd bit line sensing.
Solution Approach 2:
The patent implements periodic action through alternating sensing operations between even and odd bit line pairs. By systematically switching between even and odd bit line sensing in a periodic manner, the system achieves both noise isolation (improving reliability) and efficient utilization of bit line resources (reducing overall read time).
2Object-affected harmful factors
If only one set of bit lines (even or odd) is accessed during each read operation, then bit line coupling noise is reduced, but read throughput is decreased
Solution Approach 1:
The patent applies segmentation by dividing the bit line array into distinct even and odd pairs, where each pair can be independently sensed. This segmentation allows simultaneous or alternating sensing operations on multiple bit line pairs, increasing read throughput while maintaining noise isolation between segments through the paired architecture.
Solution Approach 2:
The patent merges even and odd bit lines into paired structures that share common sensing resources. By combining the pre-charge functionality and sensing circuitry for both even and odd bit lines in each pair, the system achieves efficient resource utilization that improves throughput while the paired configuration naturally provides noise isolation.
3Loss of time
If pre-charge time is reduced to improve read time, then read throughput is improved, but pre-charge voltage stability may be compromised
Solution Approach 1:
The patent performs the pre-charge action preliminarily for both even and odd bit lines before the sensing operation begins. This preliminary pre-charge ensures that both bit lines reach stable voltage levels in advance, allowing the actual sensing to start immediately without compromising voltage stability while minimizing the time impact on read throughput.
Solution Approach 2:
The patent establishes equipotentiality by charging both even and odd bit lines to the same voltage level before sensing. This equalization of voltage levels across paired bit lines ensures stable operating conditions for the sensing circuitry while enabling synchronized operation that reduces overall read time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances read time efficiency by reducing capacitive coupling loading between adjacent bit lines, allowing for faster sensing operations in both even and odd bit line pairs.
Implementation Method 1
reducing the capacitive coupling loading between adjacent global bit lines
Data Source
AI summary
A sensing method for a flash memory to improve read time of separate sensing in each bit line pair is introduced herein. The sensing method improves read time of even/odd BL separate sensing by, for example, charge time saving for sensing each of the bit lines during reading. In the method, both of the even bit line and the odd bit line are charged to a charge level. The voltage level of the odd bit line is maintained at the charge level and memory cells associated with the even bit line are sensed for reading data stored in the memory cells. The voltage level of the even bit line is discharged to ground, and the voltage level of the odd bit line is maintained at the charge level and sensed for reading data stored in the memory cells associated with the odd bit line.