Flash Memory Bit Line Charging via Switched Power Sources
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Solution Overview
Problem
Conventional NAND flash memory devices require on-chip charge pump circuits to provide higher voltages, leading to increased chip size and cost, as well as inefficiencies in power consumption and the need to prevent unselected memory cells from being programmed, which complicates the bit line voltage management.
Innovation Solution
A flash memory device and bit line charging method that uses a selection switch and two power sources to manage bit line voltages, where the first power source pulls up both global and local bit lines during a first time period and the second power source pumps up the local bit line voltage during a second time period, inhibiting unprogrammed memory cells without the need for an extra power source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If charge pump circuits are disposed on-chip to provide higher voltages, then the flash memory device can achieve higher voltage operation, but the chip area increases and cost increases
Solution Approach 1:
The patent extracts the charge pump function from a dedicated on-chip circuit and implements it using the existing power source and bit line structure. By turning off the selection switch during programming, the local bit line voltage is pumped up to a higher voltage level without requiring a separate charge pump circuit, thus eliminating the need for additional on-chip voltage generation hardware.
Solution Approach 2:
The patent makes the bit line structure serve multiple functions: it acts as both a signal transmission line and a voltage pumping mechanism. The same bit line that carries programming signals also serves as the medium for voltage multiplication when the selection switch is turned off, eliminating the need for dedicated voltage generation circuits.
2Power
If charge pump circuits are disposed on-chip to provide higher voltages, then the flash memory device can achieve higher voltage operation, but the power consumption efficiency deteriorates
Solution Approach 1:
The patent employs a self-service mechanism where the programming operation itself generates the higher voltage needed for inhibition. When the selection switch is turned off during programming, the bit line voltage is automatically pumped up to a higher level, eliminating the need for a separate power-consuming charge pump circuit and achieving voltage multiplication through the programming process itself.
3Reliability
If bit line voltage is not well controlled, then unselected memory cells may be accidentally programmed, but complex voltage management is required
Solution Approach 1:
The patent employs dynamic control of the selection switch to manage bit line voltage. The switch is turned on during normal operation to maintain standard voltage levels, and turned off during programming to automatically pump up the voltage to inhibition levels. This dynamic switching mechanism provides simple yet effective voltage management that ensures programming accuracy without complex control circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the circuit size and enhances efficiency by eliminating the need for an additional power source to generate higher voltages, effectively inhibiting unprogrammed memory cells and improving power efficiency.
Implementation Method 1
the first power source pulls up voltages on the global bit line and the local bit line to a first voltage
Implementation Method 2
a word line voltage on the first word line is pulled up to pump up the voltage on the local bit line to a second voltage
Data Source
AI summary
A flash memory device includes a memory string, a selection switch, a first power source and a second power source. The memory string has a plurality of memory cells. A first memory cell in the memory string is coupled to a first word line, and the first word line is selected to be a programmed word line and the first memory cell is selected to be an inhibited cell, during a first time period, the selection switch is turned on according to a selection signal, and the first power source pulls up voltages on the global bit line and the local bit line to a first voltage. During a second time period, the selection switch is turned-off according to the selection signal, a word line voltage on the first word line is pulled up to pump up the voltage on the local bit line to a second voltage.