Flash Memory Bit Line Voltage Control for CSL Stability
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Solution Overview
Problem
Conventional flash memory devices experience broadening of threshold voltage distributions due to variations in common source line (CSL) voltage during program-verify and read operations, caused by parasitic capacitances, which affects the accuracy of data storage and retrieval.
Innovation Solution
A flash memory device with a data input/output circuit that maintains program data and controls the voltage level on the bit line during program-verify operations, reducing current differences and stabilizing the CSL voltage between program-verify and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional flash memory performs program-verify and read operations without controlling bit line voltage, then the operations can be executed simply, but the CSL voltage varies due to parasitic capacitances causing broadening of threshold voltage distributions
Solution Approach 1:
The patent changes the voltage parameter of the bit line dynamically during program-verify operations. The data input/output circuit controls the bit line voltage to match the CSL voltage level, thereby preventing CSL voltage variations caused by parasitic capacitances and maintaining stable threshold voltage distributions in memory cells
Solution Approach 2:
The data input/output circuit monitors the program data state and provides feedback control to adjust the bit line voltage accordingly. This feedback mechanism ensures that the bit line voltage is optimized based on the actual programming state, preventing CSL voltage drift and maintaining measurement accuracy
2Device complexity
If the CSL voltage is allowed to vary during program-verify operations, then the circuit complexity is reduced, but the threshold voltage distributions broaden affecting data accuracy
Solution Approach 1:
The data input/output circuit is designed to perform multiple functions: it stores program data, controls bit line voltage during programming, and maintains voltage stability during program-verify operations. This multi-functionality allows the same circuit to prevent CSL voltage variations without adding separate dedicated control circuits
Solution Approach 2:
The data input/output circuit acts as an intermediary between the bit line and the memory cells during program-verify operations. It mediates the voltage control by adjusting the bit line voltage based on program data, thereby preventing direct CSL voltage variations from affecting memory cell threshold distributions
3Productivity
If no voltage control is applied during program-verify, then the operation is faster and simpler, but current differences cause CSL voltage changes that broaden threshold voltage distributions
Solution Approach 1:
The data input/output circuit prepares and maintains the bit line voltage in advance during the programming phase, so that when program-verify operations are performed, the voltage is already optimized. This preliminary voltage control prevents CSL voltage variations during verify operations, maintaining threshold voltage distribution separation without significantly impacting operation speed
Data Source
AI summary
Disclosed is a flash memory device and a program-verify method. The flash memory device includes; a plurality of memory cells connected between a bit line and a common source line, and a data input/output circuit connected to the bit line and configured to store program data for a selected one of the plurality memory cells. The data input/output circuit maintains the program data during a program-verify operation and controls a voltage level on the bit line in accordance with the program data.