Flash Memory Bit-State Mapping for Reliability and Speed
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Solution Overview
Problem
Flash memory systems face a trade-off between data reliability and write/read speed due to the use of code modulation schemes, which can lower system performance by reducing write and read speeds.
Innovation Solution
A bit-state mapping method that maps m-bit data onto 2m states through subset partitioning operations, where adjacent states are processed as one state at lower levels and distinguished at higher levels, optimizing error correction capacity and data reliability while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If code modulation schemes are used to improve data reliability through error correction code and signal mapping, then data reliability is improved, but write and read speeds are lowered resulting in reduced system performance
Solution Approach 1:
The patent divides the m-bit data into multiple subsets at different levels (first to (m-1)th levels), where each subset is processed separately. This segmentation allows the system to apply error correction codes to smaller units, improving reliability while reducing the overall complexity of the mapping process and enabling faster write and read operations.
Solution Approach 2:
The patent introduces a hierarchical level structure (first to (m-1)th levels) for organizing and processing data subsets. By adding this dimensional organization, the system can process data in a structured manner that improves reliability through multiple layers of error correction while maintaining efficient write and read speeds through the hierarchical approach.
2Reliability
If code modulation schemes are used to improve data reliability, then error correction capability is enhanced, but device complexity increases due to more complex data mapping and error correction processes
Solution Approach 1:
The patent segments the complex error correction process into multiple manageable levels, where each level handles a specific subset of data. This segmentation reduces the complexity of individual processing stages while maintaining overall error correction capability, as each level can be implemented independently with standardized procedures.
Solution Approach 2:
The patent employs dynamic subset selection and processing at different levels, where the system can adaptively choose which subsets to process and how to allocate error correction resources. This dynamic approach optimizes the balance between error correction capability and processing complexity, allowing the system to adjust to different data conditions and error patterns.
Data Source
AI summary
Disclosed is a bit-state mapping method of a flash memory system which maps m-bit data (m being a natural number more than 2) onto one of 2m states (voltage threshold distributions). The bit-state mapping method includes performing a subset partitioning operation during first to (m−1)th levels under a condition that two adjacent states are processed as one state; and distinguishing between the adjacent states while processing an (m)th level.