Flash Memory Bitline Interference Reduction via Segmented Page Buffers
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Solution Overview
Problem
Flash memory devices face performance limitations due to interference between adjacent bitlines during read and program operations, which can lead to malfunctions and inefficiencies in data sensing and storage.
Innovation Solution
The implementation of a method where data is sensed and stored in alternating odd and even page buffers connected to odd and even bitlines, allowing for separate sensing operations on each set of bitlines to prevent interference and improve read and program operations by dividing large pages into smaller units for independent data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is sensed from all memory cells simultaneously using a common wordline, then the read operation speed is improved, but interference between adjacent bitlines causes malfunctions and reduces reliability
Solution Approach 1:
The patent divides the bitline array into first and second groups of bitlines, with corresponding first and second page buffers. By segmenting the sensing operation into separate groups that can be performed independently without mutual interference, the patent enables faster parallel sensing while maintaining reliability through isolated operation of each group.
2Device complexity
If large pages are processed as single units, then the simplicity of data transfer is maintained, but the efficiency of data sensing and storage operations is reduced
Solution Approach 1:
The patent divides large pages into smaller page units that can be independently sensed and transferred. Each page unit is associated with specific bitline groups and page buffers, enabling parallel processing of multiple smaller units rather than processing one large page at a time, thereby improving overall sensing efficiency while maintaining manageable complexity.
Solution Approach 2:
The patent enables dynamic selection and independent operation of different page buffer groups based on data access patterns. The system can flexibly activate first page buffers, second page buffers, or both simultaneously depending on the specific read or program operation requirements, optimizing productivity without excessive complexity.
3Reliability
If alternating odd and even page buffers are used for separate sensing operations, then interference between bitlines is reduced, but the device complexity increases
Solution Approach 1:
The patent implements segmentation by dividing page buffers into alternating odd and even groups, each connected to corresponding bitline groups. This segmentation isolates sensing operations to prevent interference while using a regular, predictable pattern that minimizes control complexity compared to arbitrary divisions.
Data Source
AI summary
A flash memory device comprises alternately arranged odd and even memory cells. The odd and even memory cells are connected to corresponding odd and even bitlines, which are connected to corresponding odd and even page buffers. In a read operation of the flash memory device, data is sensed at two different times via the odd and even bitlines. In certain embodiments, data is read from the odd page buffers while data is being sensed via the even bit lines, or vice versa.