Flash Memory Bitline Junction Polymer Spacer TPD Reduction
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Solution Overview
Problem
As semiconductor memory devices are scaled down, they face challenges with hot electrons generated during programming causing transport program disturb (TPD) due to close spacing between adjacent memory cells, leading to interference and programming errors.
Innovation Solution
The implementation of memory devices with bit line openings and dielectric layers in the semiconductor substrate, along with first and second bit lines, enhances electrical isolation between memory cells, minimizing short channel effects and preventing TPD. This is achieved through the formation of bit line trenches, polymer spacers, and varying dopant concentrations in the bit lines to create deeper junctions and block hot electrons.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down to achieve higher circuit density, then memory capacity and access speed are improved, but hot electrons generated during programming can reach adjacent memory cells causing TPD
Solution Approach 1:
A polymer spacer is introduced as an intermediary material between adjacent bit lines and memory cells. This spacer acts as a physical barrier that blocks hot electrons generated during programming from reaching adjacent memory cells, thereby preventing TPD while allowing the scaled-down device dimensions to be maintained for high density
2Productivity
If close spacing between adjacent memory cells is used to increase density, then circuit density is improved, but electrical isolation between cells deteriorates leading to TPD
Solution Approach 1:
The polymer spacer serves as a mediating structure that provides electrical isolation between closely spaced memory cells. By positioning the spacer at the bit line junction, it creates an effective barrier that maintains electrical isolation even when cells are densely packed
Solution Approach 2:
The polymer spacer is selectively placed at specific locations where bit lines intersect and where hot electron generation is most problematic. This localized approach provides enhanced isolation precisely where needed without affecting the overall high-density layout of the memory array
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces TPD by improving electrical isolation and preventing hot electron interference between memory cells, thereby enhancing the reliability and performance of memory devices, especially in high-density memory arrays.
Implementation Method 1
By using a polymer spacer and a bit line trench in a bit line junction, the method can provide methods of making memory devices having improved TPD characteristics
Implementation Method 2
The bit line opening extends into the semiconductor substrate and contains a bit line dielectric. By the bit line dielectric in the bit line opening that extends into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells
Implementation Method 3
forming second bit lines in the semiconductor substrate under the bit line openings, the second bit lines are formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit lines
Data Source
AI summary
Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.