Flash Memory Block Information Caching for Read Speed

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing flash memory management methods, such as the flash ROM management method and flash memory driving method, result in increased access times and decreased processing speed due to the need to rewrite entire blocks during file deletion or update, and frequent re-entry of sectors between cache and flash memory.

Innovation Solution

A data read apparatus that includes a nonvolatile memory with block information for file management, a volatile memory, and a processor that reads and registers block information and file management information, allowing for efficient data retrieval and updating by utilizing a cache memory to reduce the number of direct accesses to the flash memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If FAT information is stored in the first sector of the flash memory for all other sectors, then data management is simplified, but the number of access/write times to this sector increases considerably, leading to decreased processing speed

Engineering Contradiction:
Improvedata management complexityVSAvoidprocessing speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the flash memory into multiple blocks, with each block containing its own FAT information for managing sectors within that block. This segmentation allows each block to independently manage its sectors without requiring frequent accesses to a centralized FAT table, thereby reducing access conflicts and improving processing speed while maintaining simplified data management within each block.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the entirety of one block is rewritten to update management information during file deletion or update, then data integrity is maintained, but the number of read, erase and write operations increases, leading to decreased processing speed

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the FAT information from the entire block and places it in a dedicated management area within the same block. This allows only the necessary management information to be updated during file operations, rather than rewriting the entire block. The extraction of FAT information enables selective updates that maintain data integrity while significantly reducing the number of read, erase, and write operations required.

Inventive Principle:
Principle #2Taking out (Extraction)

3Adaptability or versatility

If sector re-entry between cache memory and flash memory is executed frequently during write/read operations, then data access flexibility is improved, but the number of access times to flash memory increases, leading to decreased processing speed

Engineering Contradiction:
Improvedata access flexibilityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent performs preliminary actions by pre-loading FAT information into the cache memory during initialization or when blocks are first accessed. This preliminary caching of management information reduces the need for frequent re-entry operations between cache memory and flash memory during subsequent data access operations. The pre-positioned FAT information in cache memory enables faster data retrieval while maintaining access flexibility, thereby improving processing speed without sacrificing adaptability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10120791B2Data read apparatus, data read method, and storage medium storing data read program
Publication Date: 2018.11.06 CASIO COMPUTER CO LTD
  • US10120791B2 patent drawing
  • US10120791B2 patent drawing
  • US10120791B2 patent drawing

AI summary

A data read apparatus includes a nonvolatile memory comprising a plurality of blocks, each of the blocks including an area storing block information, in which a position of a next block is written, or storing the block information and file management information, and an area storing actual data; a volatile memory; a power-on circuit configured to turn on supply of power to the nonvolatile memory and the volatile memory; and a processor. The processor is configured to: read out the block information stored in each of the blocks of the nonvolatile memory, or the block information and the file management information, when the supply of power was turned on by the power-on circuit, and register the read-out block information, or the block information and the file management information, in the volatile memory as file position information.