Flash Memory Block Erase Partitioning for Tunnel Oxide Protection
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Solution Overview
Problem
The existing block erase method for flash memory is prone to overerase due to tailing bits, leading to increased stress on the tunnel oxide layer and reliability issues, as well as prolonged erase times and failed verification.
Innovation Solution
A block erase method that partitions a block into smaller blocks and adjusts the erase step threshold values to perform byte-by-byte erase verification, allowing for dynamic adjustment of block size based on erase step, thereby reducing overerase and erasing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block erase is performed on the entire flash memory by block, then the erase operation covers all memory cells, but tailing bits cause excessive erase and increased stress on the tunnel oxide layer
Solution Approach 1:
The patent divides the flash memory into multiple segments based on erase step characteristics: fast erase regions, slow erase regions, and tailing bit regions. By segmenting the erase operation and applying different strategies to each segment (such as early termination for fast regions and targeted re-erase for tailing bits), the patent reduces excessive erase cycles on reliable cells while maintaining thorough erasure of problematic cells, thereby improving tunnel oxide layer reliability without significantly sacrificing overall erase speed.
Solution Approach 2:
The patent implements dynamic adjustment of erase operations by monitoring erase verification results in real-time. The erase process adapts its behavior based on detected tailing bits and erase step performance, dynamically adjusting which blocks require re-erase and how many times. This dynamic approach prevents static over-erasing of all blocks while ensuring problematic areas receive adequate erase cycles, resolving the contradiction between reliability and productivity.
2Reliability
If block erase is performed repeatedly due to erase verification failure, then tailing bits are addressed, but the erasing time is prolonged and tunnel oxide layer stress increases
Solution Approach 1:
The patent performs preliminary classification of blocks into fast erase, slow erase, and tailing bit categories during the initial erase sweep. By identifying tailing bit blocks early and marking them for targeted re-erase, the patent avoids unnecessary repeated full-block erases. This preliminary action enables selective re-erase only where needed, significantly reducing total erase time while ensuring verification success for problematic blocks.
Solution Approach 2:
The patent applies different erase strategies to different local regions based on their erase characteristics. Fast erase blocks use early termination, slow erase blocks receive extended erase cycles, and tailing bit blocks undergo targeted re-erase. This local quality approach ensures each region receives appropriate erase treatment, achieving verification success without uniformly prolonging the entire erase process.
3Device complexity
If block erase is performed with fixed block size, then the process is simple, but tailing bits cause overerase and increased stress on tunnel oxide layer
Solution Approach 1:
The patent segments the flash memory into distinct erase categories (fast, slow, tailing bit) and applies different erase strategies to each segment. This segmentation enables differentiated treatment that protects reliable cells from over-erase while ensuring thorough erasure of problematic cells, improving tunnel oxide layer durability with manageable complexity through systematic classification.
Solution Approach 2:
The patent changes erase parameters dynamically based on detected block characteristics. Erase voltage, pulse width, and re-erase count are adjusted according to whether a block is classified as fast erase, slow erase, or tailing bit. These parameter changes enable tailored erase treatment that protects tunnel oxide layer durability while maintaining process feasibility.
Data Source
AI summary
A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.