3D Flash Memory Block Segmentation to Prevent Cross-Layer Disturbance
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Solution Overview
Problem
In flash memory devices with 3D stack structures, the sharing of a decoder among multiple semiconductor layers can lead to disturbances and undesired soft programming during program and erase operations, limiting the ability to control memory blocks separately and affecting the storage capacity and integration.
Innovation Solution
The implementation of a flash memory device with vertically stacked layers, where memory cells from different layers are electrically coupled through shared wordlines, allowing a single row decoder to supply a common voltage, and transistors are controlled based on address bits to prevent cross-talk during operations, ensuring separate control of memory blocks and reducing the likelihood of soft programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single row decoder is shared across multiple semiconductor layers to reduce chip size, then device complexity is reduced, but disturbances and undesired soft programming occur during program and erase operations
Solution Approach 1:
The patent segments the memory blocks into different groups associated with each semiconductor layer. Each memory block is assigned to a specific layer, allowing the shared row decoder to selectively activate wordlines in only the intended layer during program and erase operations. This segmentation prevents cross-layer interference and soft programming while maintaining the benefits of a shared decoder structure.
2Quantity of substance
If multiple semiconductor layers are stacked to increase memory capacity, then storage density is improved, but disturbances occur during program and read operations in adjacent layers
Solution Approach 1:
The patent applies local quality by assigning specific memory blocks to specific semiconductor layers. During program operations, the row decoder activates wordlines only in the target layer while keeping wordlines in other layers inactive. This localized control ensures that program disturbances are confined to the intended memory block and do not affect adjacent layers, thereby increasing memory capacity without introducing cross-layer interference.
3Ease of operation
If wordlines in different layers are electrically coupled to enable shared decoder control, then ease of operation is improved, but undesired soft program is generated during erase operations
Solution Approach 1:
The patent implements preliminary action by pre-assigning memory blocks to specific semiconductor layers. Before erase operations begin, the row decoder is configured to activate wordlines only in the layer containing the target memory block, while keeping wordlines in other layers inactive. This preliminary selective activation prevents the generation of soft programs in unselected layers during erase operations, maintaining ease of operation through shared decoder control while eliminating harmful cross-layer effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration and operating performance of flash memory devices by preventing disturbances and soft programming, allowing for improved program, read, and erase operations across multiple layers, thereby increasing memory capacity and efficiency.
Implementation Method 1
NAND flash memory has a structure in which at least two cell transistors are connected in series to one bitline, and stores and erases data by using a Fowler-Nordheim (F-N) tunneling method.
Data Source
AI summary
Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.