Flash Memory Block Segmentation for Optical Transceiver Rewrite Speed
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Solution Overview
Problem
Existing optical transceivers face challenges in efficiently rewriting flash memory within the restricted time frame set by standards like SFP+, as the conventional process of erasing and writing in flash memory blocks often exceeds the allowed time due to inherent flash memory characteristics and system specifications.
Innovation Solution
Implementing a method where flash memory is divided into two blocks, each in active and inactive modes, allowing for asynchronous erasure and writing, where the inactive block is prepared before new data is received, and data is rearranged in RAM before being written to the inactive block, decoupling the erase and write processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional process of erasing and writing flash memory blocks is used, then the flash memory can be rewritten, but the process time exceeds the SFP+ standard limit of 40mS
Solution Approach 1:
The patent applies preliminary action by erasing the inactive block in advance before new data needs to be written. The system maintains two blocks (active and inactive) and erases the inactive block beforehand, so when data needs to be rewritten, the erased block is already ready to receive data immediately, eliminating the sequential wait time for erasure completion.
Solution Approach 2:
The patent segments the flash memory into two distinct blocks: an active block and an inactive block. This segmentation allows parallel operations where one block is being used for data storage while the other is being erased or prepared, enabling overlapping of erasure and write operations that reduces total rewriting time.
2Ease of operation
If data is written directly to flash memory blocks, then the writing process is simple, but the erasure and writing must be done sequentially which increases total time
Solution Approach 1:
The patent introduces an intermediary mechanism by using the inactive block as a buffer between data reception and active storage. Data can be prepared and transferred to the inactive block while the active block is still being used, and then the blocks are swapped, allowing overlapping operations that improve throughput without complicating the basic write interface.
Data Source
AI summary
An effective algorithm for the CPU with a flash memory is disclosed to shorten a dead time to erase the flash memory and to write new data therein. The flash memory of the invention provides front and back blocks for the user data area. When the front block is filled, the back block is erased just after the front block is fully filled in advance to receive a new data next to be written.