Flash Memory Block Selection Circuit Area Reduction
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Solution Overview
Problem
Conventional flash memory devices have a large block selection circuit that occupies significant area due to the number of transistors used, which is undesirable for reducing the size of the flash memory device.
Innovation Solution
A reduced block selection circuit design using fewer logic gates, specifically incorporating a NAND gate and an inverter, to control the enabling or disabling of memory blocks by decoding block address signals and employing switching means operated by a precharge control signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional block selection circuit with multiple NAND gates and a block fuse is used, then bad blocks can be reliably disabled, but the circuit occupies significant area
Solution Approach 1:
The patent merges the block fuse function into the block selection circuit by using the same transistor structure for both address decoding and block disabling. The block selection circuit uses a reduced number of NAND gates (first and second NAND gates) that serve dual purposes: decoding block addresses and disabling bad blocks through the block fuse connection, eliminating the need for separate disabling circuitry
Solution Approach 2:
The patent extracts the essential function of block disabling from the conventional complex circuit structure. By removing unnecessary logic gates and simplifying the circuit to only the essential NAND gates needed for address decoding, the block fuse integration becomes the primary mechanism for disabling bad blocks, reducing overall circuit area
2Area of stationary object
If the number of transistors in the block selection circuit is reduced, then chip size decreases, but circuit functionality may be compromised
Solution Approach 1:
The block selection circuit transistors are designed to perform multiple functions simultaneously. The first and second NAND gates share transistors with the block fuse structure, allowing the same hardware components to handle both address decoding for normal blocks and disabling signals for bad blocks, maintaining full functionality with fewer transistors
Solution Approach 2:
The circuit uses dynamic control signals (PGMPREb and EN) that change state based on operation mode (program or read). The block selection circuit adapts its behavior dynamically: during program operations, it responds to PGMPREb signals; during read operations, it responds to EN signals. This dynamic operation allows the simplified circuit to maintain versatility across different operational contexts
Data Source
AI summary
The present invention relates to a block selection circuit of a flash memory device. The block selection circuit includes a control signal output unit, switching means, and an operation controller. The control signal output unit outputs a control signal for enabling or disabling memory blocks connected thereto by employing block address signals. The block address signals are decoded according to an input address and provided. The switching means switches the control signal so that the control signal is input as a block selection control signal. The operation controller turns off drain and source select transistors of a memory block connected thereto according to a logic level of a first control signal.