Flash Memory Block Sizing via Word Line Bias Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices have a fixed memory cell block size determined by their physical structure, limiting adaptability to different applications, as the size cannot be changed post-fabrication, making them unsuitable for varying data processing demands.
Innovation Solution
The flash memory device allows for selective change in memory cell block size by adjusting the number of global word lines during an erase operation using block size change signals, without altering its physical structure, through an X-decoder that generates block selection signals and word line bias voltages to connect global word lines to memory cell blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory cell block size is fixed by physical structure, then manufacturing reliability is improved, but adaptability to different applications deteriorates
Solution Approach 1:
The patent implements dynamic block size selection by introducing control logic that can selectively activate different numbers of global word lines (e.g., 32, 64, or 128 pages per block) based on application requirements. This allows the flash memory device to adapt its memory cell block size dynamically without changing the physical structure, resolving the contradiction between manufacturing reliability and application adaptability.
Solution Approach 2:
The patent changes the operational parameter of block size by controlling the number of global word lines activated during erase operations. Through control signals, the system can configure memory cell blocks to include different numbers of pages (32, 64, or 128), effectively changing the block size parameter without physical modification, thus achieving adaptability while maintaining manufacturing reliability.
2Quantity of substance
If the number of global word lines is increased, then the memory cell block size is increased, but the device complexity increases
Solution Approach 1:
The patent designs global word lines with multi-functionality, where the same physical global word lines can serve different block size configurations (32, 64, or 128 pages per block) depending on control signals. This universal design allows the system to achieve variable block sizes without adding dedicated hardware for each configuration, thereby increasing storage capacity while minimizing the increase in device complexity.
Solution Approach 2:
The system dynamically configures the number of active global word lines based on control signals, allowing the memory cell block size to be adjusted without permanently increasing device complexity. The same hardware infrastructure supports multiple block sizes through dynamic activation, avoiding the need for additional physical components for each configuration.
3Ease of operation
If the memory cell block size is reduced, then the ease of operation for small data processing is improved, but the productivity for large data processing deteriorates
Solution Approach 1:
The patent implements dynamic block size selection that allows the system to switch between small block sizes (32 pages) for ease of operation in small data processing applications and large block sizes (128 pages) for high productivity in large data processing applications. This dynamic adaptability resolves the contradiction by allowing the optimal block size to be selected based on the specific operational requirements.
Solution Approach 2:
The system changes the block size parameter dynamically based on application needs, using control logic to configure appropriate block sizes. For small data processing, smaller blocks improve ease of operation, while for large data processing, larger blocks enhance productivity, with the parameter being adjustable without physical changes.
Data Source
AI summary
A flash memory device and an erase method thereof, in which the size of a memory cell block can be selectively changed during an erase operation. The flash memory device includes a plurality of memory cell blocks, an X-decoder, and a plurality of block selection units. The X-decoder decodes block address signals, page address signals, and block size change signals in response to one of a program command, a read command, and an erase command, generates a plurality of block selection signals and word line bias voltages according to the decoding result, and outputs the word line bias voltages to a plurality of global word lines, respectively. During the erase operation, the size of an erased memory cell block is decided according to word line bias voltages output from the X-decoder. During the erase operation, at least one of the plurality of block selection units selects at least one of the plurality of memory cell blocks. Accordingly, the size of a memory cell block of a flash memory device can be changed in various ways depending on operating characteristics of products.