Flash Memory Buffer Region Segmentation for Speed and Reliability
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Solution Overview
Problem
The reliability of Multi-Level Cell (MLC) flash memory devices is reduced due to increased coupling effects between memory cells, leading to shifting and expansion of threshold voltage distributions, which causes read data errors and requires iterative reprogramming methods to refine voltage distributions, while conventional On-chip Buffered Programming approaches are slow due to multiple write/read operations.
Innovation Solution
A flash memory device array with a main region and a buffer region divided into a first and second buffer region, where buffer data is stored in the first region for reliability mode and the second region for high-speed mode, using control logic to manage the page buffer operations, allowing for selective storage based on mode to balance programming speed and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple data bits are programmed in flash memory cells, then storage capacity is improved, but threshold voltage distribution shifts and expands causing read errors
Solution Approach 1:
The flash memory cell array is divided into multiple sub-regions, each capable of storing different data bits. By segmenting the storage space and using separate verify operations for each sub-region, the system can program multiple bits while maintaining better control over threshold voltage distributions, reducing the coupling effects that cause distribution shifts and expansions.
2Productivity
If conventional On-chip Buffered Programming is used, then programming is performed, but programming speed is reduced due to multiple write/read operations
Solution Approach 1:
The patent combines multiple write and verify operations into a single unified programming process. Instead of performing separate write and read operations for each data bit, the system performs parallel programming across multiple sub-regions and uses a unified verify operation, significantly reducing the total number of operations and improving programming speed while maintaining data integrity.
3Reliability
If iterative reprogramming is performed to refine voltage distributions, then read accuracy is improved, but programming time increases
Solution Approach 1:
The patent performs preliminary verification operations during the programming process itself, rather than requiring separate iterative reprogramming cycles. By verifying each sub-region immediately after programming and adjusting voltages in real-time, the system achieves accurate threshold voltage distributions in a single programming pass, eliminating the need for time-consuming iterative reprogramming while maintaining high read accuracy.
Data Source
AI summary
Disclosed is a flash memory device and programming method that includes; receiving buffer data and determining between a high-speed mode and a reliability mode for buffer data, and upon determining the reliability mode storing the buffer data in a first buffer region, and upon determining the high-speed mode storing the buffer data in a second buffer region. The memory cell array of the flash memory including a main region and a separately designated buffer region divided into the first buffer region and second buffer region.