Flash Memory Byte Access via Progressive Indexing

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Solution Overview

Problem

Flash memory devices face limited endurance due to frequent write operations, leading to sector degradation, and existing wear-leveling techniques increase complexity and cost, especially when trying to achieve high-speed byte access and data preservation.

Innovation Solution

A method for managing flash memory using a data structure with an index field and a data field, allowing for high-speed byte access by programming data in empty segments without sector erase operations, and utilizing a status field to manage data structure status and address translation, enabling efficient write operations and extending device endurance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional flash memory write operations are used, then data can be stored, but sector endurance is limited due to frequent erase operations

Engineering Contradiction:
Improvesector enduranceVSAvoidwrite operation frequency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the flash memory sector into multiple sub-sectors or pages, allowing write operations to be performed on individual pages without erasing the entire sector. This enables frequent writes to specific regions while preserving other regions, thereby extending overall sector endurance while maintaining high write productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-erasing only the specific sub-sector or page where data will be written, rather than erasing the entire sector in advance. This selective pre-erasure approach reduces the frequency of full sector erase operations, extending endurance while allowing frequent writes to occur.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If EEPROM is used for high-speed byte access, then byte-by-byte programming and erasing is enabled, but memory density and cost-effectiveness decrease

Engineering Contradiction:
Improvebyte access speedVSAvoidmemory density
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent makes flash memory multi-functional by enabling it to perform both high-speed byte-by-byte access operations and maintain high memory density. Through the described data structure and address mapping techniques, flash memory can emulate EEPROM-like byte access while preserving its inherent high-density advantage, making it universally suitable for both application types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the operational parameters of flash memory by implementing byte-addressable access modes and selective erase capabilities. This allows flash memory to operate with byte-level granularity similar to EEPROM, while maintaining its high-density physical structure, thus achieving both fast byte access and high memory capacity.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If wear-leveling techniques with counters are implemented, then sector wear is distributed evenly, but device complexity increases

Engineering Contradiction:
Improvedevice lifetimeVSAvoidwear-leveling mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses a simplified wear-leveling approach that copies or relocates data between sectors based on wear status, avoiding the need for complex counter-based tracking systems. This data relocation method distributes wear more evenly across sectors while using simpler management logic, reducing device complexity while extending overall device lifetime.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent implements a self-service wear-leveling mechanism where the flash memory system automatically manages its own wear distribution through intelligent sector selection and data relocation, without requiring external controller intervention or complex monitoring infrastructure. This reduces overall system complexity while maintaining extended device lifetime.

Inventive Principle:
Principle #25Self-service

4Reliability

If mapping tables are continuously updated to track data locations, then data integrity is preserved, but performance decreases due to slow erase cycles

Engineering Contradiction:
Improvedata integrityVSAvoidupdate speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies partial action by updating mapping information only for the specific sub-sectors or pages that have been modified, rather than updating entire sector mappings. This selective update approach maintains data integrity for changed regions while minimizing the performance impact of mapping updates, allowing faster overall system operation despite continuous tracking requirements.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8239619B2Method and apparatus for high-speed byte-access in block-based flash memory
Publication Date: 2012.08.07 MACRONIX INTERNATIONAL CO LTD
  • US8239619B2 patent drawing
  • US8239619B2 patent drawing
  • US8239619B2 patent drawing

AI summary

Techniques utilizing an erase-once, program-many progressive indexing structure manage data in a flash memory device which avoids the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. Consequently, block-based flash memory can be used for high-speed byte access.