Flash Memory Module Programming Acceleration via Cache Copy-Back
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-level cell flash memory systems, the programming speed is bottlenecked by the host interface during most significant bit (MSB) programming and by the flash memory module during least significant bit (LSB) programming, leading to inefficiencies, especially in devices with limited internal volatile memory.
Innovation Solution
A method is introduced where data units are first level programmed to cache memory pages using faster MSB programming and then second level programmed to target memory pages using slower LSB programming, with a copy back operation, optimizing the allocation of cache and target pages to balance caching and copy-back processes, thereby accelerating data programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If MSB programming is performed, then programming speed is improved, but host interface becomes a bottleneck
Solution Approach 1:
The patent introduces an intermediary buffer memory between the host interface and the flash memory module. This buffer temporarily stores data units during MSB programming, decoupling the host interface from the programming process and eliminating it as a bottleneck. The buffer acts as a mediator that allows MSB programming to proceed at high speed without being constrained by host interface limitations.
2Manufacturing precision
If LSB programming is performed, then data is programmed to target pages, but flash memory module becomes a bottleneck
Solution Approach 1:
The patent segments the programming process into two distinct phases: MSB programming phase and LSB programming phase. During MSB programming, data units are programmed to cache memory pages with high speed. After MSB programming completes, a copy-back operation retrieves the data and performs LSB programming to target pages. This segmentation allows each phase to optimize for its specific requirements, improving overall productivity.
Solution Approach 2:
The patent performs preliminary MSB programming to cache memory pages before performing the final LSB programming to target pages. This preliminary action establishes data in a temporary location where it can be processed at higher speed, and then copied to the final target pages when ready, optimizing the overall programming workflow.
3Productivity
If internal volatile memory is not big enough, then data buffering capability is limited, but programming acceleration is needed
Solution Approach 1:
The patent moves the buffering function from the traditional internal volatile memory dimension to the flash memory module itself by designating cache memory pages within the flash module. This dimensional shift allows the system to utilize the flash memory's capacity for buffering purposes, effectively increasing available buffer space without requiring larger volatile memory. The cache memory pages serve as a secondary buffering dimension that complements the limited volatile memory.
Data Source
AI summary
According to an embodiment of the invention there is provided a method for accelerating programming of data, the method may include receiving multiple input data units that were sent from a host computer; wherein the input data units may include first and second input data units; first level programming the first input data units to cache memory pages and first level programming the second input data units to first level target memory pages; and applying a copy back operation that comprises retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages; wherein any target page out of the first level target pages and the second level target pages differs from a cache memory page; and wherein the first level programming is faster than the second level programming.