Flash Memory Cache Read Control Logic

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Solution Overview

Problem

The complexity of control circuitry in memory systems that integrate NAND and NOR flash memories hinders efficient data transfer and programming, particularly in integrated memory architectures where program code and data storage require optimized read/write operations.

Innovation Solution

A flash memory device with a non-volatile memory core, buffer memories, and a control logic circuit that performs cache read operations by generating enable signals to copy address and command information, allowing for efficient data transfer between the non-volatile memory core and buffer memories, optimizing read/write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If NAND and NOR flash memories are integrated in a single memory system, then storage capacity and functionality are improved, but control circuitry complexity increases

Engineering Contradiction:

Improvestorage capacityVSAvoidcontrol circuitry complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory system is segmented into distinct NAND flash memory region and NOR flash memory region, each with dedicated control logic. The controller divides management responsibilities by memory type, simplifying overall control circuitry while maintaining integrated functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A buffer memory is introduced as an intermediary component between the NAND/NOR flash memories and the host system. This buffer acts as a mediator that handles data transfer and coordination, reducing the control burden on the main controller and simplifying the control circuitry architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If conventional read operations are used in integrated memory systems, then data can be retrieved from non-volatile memory, but data transfer efficiency decreases due to host transfer time

Engineering Contradiction:

Improvedata transfer efficiencyVSAvoidhost transfer time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

Data is preliminarily transferred from the non-volatile memory to the buffer memory before the host is ready to receive it. This preliminary action allows the memory system to prepare data in advance, eliminating the need for the host to wait during data transfer and significantly improving data transfer efficiency.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The buffer memory enables continuous data transfer operations by maintaining a ready supply of data. While the host is processing or transferring data, the buffer continuously receives and prepares additional data from the non-volatile memory, ensuring uninterrupted data flow and eliminating idle time.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS7353326B2Flash memory device supporting cache read operation

Publication Date: 2008.04.01 SAMSUNG ELECTRONICS CO LTD

AI summary

A flash memory device comprises a non-volatile memory core operatively connected to first and second buffer memories through a page buffer. The device further comprises a first register adapted to receive command and address information from a host system, a copy circuit adapted to copy the command and address information from the first register to a second register within a control logic circuit. The device alternately transfers information to the first and second buffer memories during a cache read operation comprising a plurality of data read operations.