Flash Memory Calibration Circuit for Read Error Reduction
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Solution Overview
Problem
Existing flash memory technologies experience errors in reading results due to discrepancies between reference and storage currents, caused by changes in memory cells due to external factors, leading to incomplete programming or excessive erasing currents.
Innovation Solution
A memory system with a calibration method that includes a reference circuit, calibration circuit, mirror circuit, clamp circuit, and comparison circuit, where calibration memory cells are programmed and erased to generate matching currents, ensuring the reference current aligns with storage currents, thereby reducing read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If reference cells are calibrated against master reference cells using existing methods, then reference signal generation is simplified, but reading result accuracy deteriorates due to errors caused by discrepancies between reference and storage currents
Solution Approach 1:
The patent applies preliminary action by performing calibration of reference memory cells before actual read operations. The calibration process pre-adjusts the reference cells to match storage cells under identical conditions, eliminating the need for complex real-time adjustments during reading. This preliminary calibration ensures that reference currents accurately represent storage cell characteristics, thereby maintaining high reading accuracy while using a relatively simple reference circuit structure.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting the reference current parameters during calibration. Specifically, the system varies programming and erasing currents applied to reference memory cells to match the operational parameters of storage cells. By changing these electrical parameters (current magnitudes, pulse durations) during the calibration phase, the system compensates for discrepancies between reference and storage cells, resolving the accuracy issue without complicating the overall circuit design.
2Measurement precision
If calibration memory cells undergo programming and erasing operations to generate matching currents, then current matching accuracy is improved, but calibration process time increases
Solution Approach 1:
The patent applies partial action by performing calibration operations on only a selected subset of memory cells rather than all cells in the array. Specifically, dedicated reference memory cells are calibrated against storage cells, and this calibration data is then used to adjust the entire reference circuit. This partial calibration approach achieves sufficient current matching accuracy without the time penalty of calibrating every cell individually.
Solution Approach 2:
The patent uses copying by creating reference memory cells that replicate the structure and characteristics of storage cells. These reference cells serve as copies that undergo controlled programming and erasing to mimic storage cell behavior. By calibrating these copied reference structures, the system achieves accurate current matching without needing to calibrate each storage cell directly, thereby reducing overall calibration time while maintaining high accuracy.
3Measurement precision
If reference memory cells are used as same as storage cells, then calibration accuracy is improved, but device complexity increases due to additional calibration circuits
Solution Approach 1:
The patent applies universality by designing reference memory cells with the same structure and characteristics as storage cells, allowing them to serve dual purposes: as storage representatives for calibration and as functional memory elements. The calibration circuits are designed to perform multiple functions - they can calibrate reference cells, generate reference currents, and adjust operational parameters. This multi-functionality reduces overall device complexity despite the added calibration capability, as the same hardware structures serve multiple roles.
Solution Approach 2:
The patent implements self-service by enabling the reference memory cells to calibrate themselves against storage cells without requiring external intervention or complex external calibration equipment. The calibration process uses the inherent characteristics of the storage cells to automatically adjust the reference cells' parameters. This self-calibrating mechanism improves accuracy while minimizing additional circuit complexity, as the system uses its own internal resources for calibration rather than requiring elaborate external calibration systems.
Data Source
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AI summary
A memory and a reference circuit calibration method are provided. The memory includes: a memory array including a plurality of memory cells; a reference circuit including a reference memory cell and a reference connection terminal, wherein the reference memory cell is a same as the memory cell; a calibration circuit including a calibration connection terminal, and a mirror circuit including a first mirror terminal and a second mirror terminal, wherein the first mirror terminal is connected to the reference connection terminal, and the second mirror terminal is connected to the calibration connection terminal; a clamp circuit, configured to set one of a voltage of the reference connection terminal and a voltage of the calibration connection terminal as a preset voltage and to set the other thereof as a comparison voltage; and a comparison circuit configured to input the comparison voltage and the preset voltage, and to output a comparison result.