Flash Memory Cell with Back Control Gate on SOI
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Solution Overview
Problem
Flash memory cells require high programming voltages, which increase design complexity and risk damage to the cells and nearby memory cells, and existing solutions like back control gates in EEPROM devices are not suitable for programming due to distance from the channel region.
Innovation Solution
A flash memory cell with a FET transistor on a semiconductor-on-insulator (SOI) substrate featuring two control gates, a front control gate and a back control gate, where the back control gate is located within the base substrate and separated from the channel by only the insulating layer, allowing for combined use in programming operations, reducing the voltage needed for programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If high programming voltage is applied to the control gate to generate hot electrons for programming, then programming operation can be performed, but the complexity of peripheral circuits increases and the risk of damaging cells increases
Solution Approach 1:
The control gate is divided into two separate gates: a front control gate and a back control gate. The back control gate is positioned close to the channel region and is used specifically for programming operations to generate hot electrons, while the front control gate handles other control functions. This segmentation eliminates the need for complex charge pump circuits by distributing functionality across two simpler gates.
Solution Approach 2:
The back control gate acts as an intermediary element positioned between the front control gate and the channel region. It mediates the programming operation by being close enough to the channel to generate hot electrons through moderate voltage application, while being separated by the insulating layer to prevent direct damage to the channel. This intermediary structure enables programming without requiring extremely high voltages at the front control gate.
2Ease of operation
If high programming voltage is applied to the control gate to generate hot electrons, then programming can be achieved, but the reliability of the memory cell decreases due to potential damage
Solution Approach 1:
By segmenting the control gate into front and back components, the programming stress is isolated to the back control gate which is designed to handle high voltage. The front control gate and channel region are protected from direct exposure to high programming voltages, reducing the risk of damage and improving overall cell reliability.
Solution Approach 2:
The back control gate serves as a protective intermediary that absorbs the stress of high voltage programming operations. It is positioned close to the channel but separated by an insulating layer, allowing it to generate the necessary hot electrons while preventing direct high voltage damage to the channel and floating gate structures.
3Ease of manufacture
If a back control gate is placed far from the channel region, then it can be formed in the base substrate, but it cannot be used for programming operations
Solution Approach 1:
The back control gate is positioned at an optimal distance from the channel region - close enough to generate hot electrons for programming but far enough to be formed in the base substrate using standard manufacturing processes. This partial proximity allows the gate to perform programming functions while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution lowers programming voltages by approximately 40%, simplifying peripheral circuit design and enhancing the reliability of the memory cell and circuit, while allowing for efficient programming and erasure operations.
Implementation Method 1
A very high voltage is applied to the control gate and to the drain. The channel is passing so that electrons flow from the source to the drain. The source-drain current is then sufficiently high for high-energy electrons (hot electrons resulting from the collision of the charges with the crystalline network of the channel) to reach the floating gate
Implementation Method 2
a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer
Implementation Method 3
A very high voltage is applied to the drain so that a high voltage, of opposite polarity to that implemented in programming, is thus applied between the control gate and the source. The electrical field between the two gates increases until electrons can escape from the floating gate through the gate dielectric layer by tunnel effect.
Data Source
AI summary
The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.