Flash Memory Cell Double Gate Structure for Multi-Bit Storage
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Solution Overview
Problem
Conventional flash memory cells, such as ETOX-type cells, face limitations in minimizing area and efficiently managing multi-bit data storage, particularly in achieving a theoretical minimum area of 8 F^2 while effectively controlling carrier channel conduction for multi-bit operations.
Innovation Solution
A multi-bit flash memory cell design featuring a double gate structure with two charge-trapping regions, doped regions, and dielectric layers, where the second charge-trapping region influences the carrier channel conduction, allowing for controlled electron injection and removal through specific voltage applications, enabling four distinct threshold voltages for data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional ETOX-type flash memory cell structure is used, then the cell can perform basic write and erase operations, but the area cannot be minimized to the theoretical minimum of 8 F^2 and multi-bit data storage efficiency is limited
Solution Approach 1:
The flash memory cell is segmented into two distinct charge-trapping regions (first and second charge-trapping regions) within the substrate, each capable of independently storing charge. This segmentation allows the cell to store multiple bits of data by varying the charge states of individual regions, enabling multi-bit storage while maintaining a compact area of 8 F^2.
Solution Approach 2:
The invention utilizes the vertical dimension by embedding charge-trapping regions within the substrate depth rather than only expanding horizontally. The charge-trapping regions are positioned at different depths and locations in the substrate, allowing multi-bit storage capability to be achieved without increasing the planar area of the cell, thus achieving the theoretical minimum area of 8 F^2.
2Device complexity
If a single charge-trapping region is used, then the cell structure is simpler, but the ability to control carrier channel conduction for multi-bit operations is insufficient
Solution Approach 1:
Each charge-trapping region is given distinct local properties and positions within the substrate, with the second charge-trapping region specifically configured to influence the conduction behavior of the carrier channel. This local differentiation allows independent control of each region's charge state, enabling precise control over carrier channel conduction for multi-bit operations while maintaining manageable device complexity.
3Reliability
If high voltage is applied for programming operation, then electron injection into charge-trapping region is effective, but energy consumption increases
Solution Approach 1:
The patent introduces a charge-trapping region as an intermediary structure between the control gate and the channel. This intermediary allows for more efficient charge transfer during programming operations, reducing the energy required compared to direct electron injection methods. The charge-trapping regions capture and hold electrons, enabling effective programming with reduced energy consumption while maintaining reliable data storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for a compact flash memory cell with a theoretical minimum area of 8 F^2, capable of storing 4-bit data by adjusting threshold voltages through controlled voltage applications, enhancing data storage efficiency and operational flexibility.
Implementation Method 1
a first charge-trapping region and a second charge-trapping region disposed in a semiconductor substrate
Implementation Method 2
the second charge-trapping region is configured to influence the conduction behavior of a carrier channel in the semiconductor substrate under the first charge-trapping region
Implementation Method 3
Consequently, a turn-on current flows between the drain region 16 and the source region 14, producing pairs of hot electrons and hot holes in the vicinity of the drain region 16. Those holes flow into the substrate 12 as a substrate current. In contrast, hot electrons are injected into the floating gate 20 to increase the threshold level
Implementation Method 4
Fowler-Nordheim tunnel current flows through the thin tunnel insulating film 18 (approximately 10 nm) provided between the source region 14 and floating gate 20. Thus, electrons are reduced from the floating gate 20 to complete the erasing operation
Data Source
AI summary
A flash memory cell according to the present invention includes a first charge-trapping region and a second charge-trapping region disposed in a semiconductor substrate, a first doped region disposed in the semiconductor substrate at a first side of the first charge-trapping region, a second doped region disposed in the semiconductor substrate at a second side of the first charge-trapping region, a first dielectric layer separating the semiconductor substrate from the first charge-trapping region and the second charge-trapping region, a first conductor disposed above the first charge-trapping region, and a second dielectric layer separating the first charge-trapping region from the first conductor, wherein the second charge-trapping region is configured to influence the conduction behavior of a carrier channel in the semiconductor substrate under the first charge-trapping region.