Flash Memory Cell Repair via Identifier Remapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In flash memory devices, particularly those with NOR architecture, a single unprogrammable cell can render an entire column unusable, leading to operational speed issues during program operations due to the inability to efficiently repair cells in real-time.
Innovation Solution
A method is introduced where single unprogrammable cells are repaired during program operations by storing an identifier and remapping data to a redundant location, with entire column repairs conducted during subsequent erase operations, utilizing a row enable indicator to manage address matching and facilitate replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If column repair is performed during program operations, then cell reliability is improved, but operation speed deteriorates due to repair time consuming the low program latency window
Solution Approach 1:
The repair operation is segmented into two distinct phases: single cell repair during program operations and column repair during erase operations. This segmentation allows each phase to operate independently with appropriate timing, preventing the repair process from blocking the low-latency program operation while still ensuring reliability through timely repair.
Solution Approach 2:
Single cell repair is performed as a preliminary action during program operations to address individual failures before they propagate. The system identifies and repairs only the affected cell during program time, then schedules column-wide repair during the subsequent erase operation, ensuring reliability without compromising program speed.
2Reliability
If entire column repair is performed during program operations, then column reliability is improved, but productivity deteriorates due to extended repair time
Solution Approach 1:
The repair process is segmented by scope and timing: single cell repair during program operations for immediate reliability, and column repair during erase operations for comprehensive maintenance. This segmentation prevents productivity loss by performing column repair during the erase cycle rather than blocking program operations.
Solution Approach 2:
Column repair is performed periodically during erase operations rather than continuously during program operations. This periodic action allows the system to maintain column reliability through scheduled maintenance windows without interfering with the continuous productivity-generating program operations.
3Reliability
If real-time cell repair is implemented, then reliability is improved, but device complexity increases due to additional repair control logic
Solution Approach 1:
The control logic leverages existing multi-functional elements: the same address matching circuitry used for normal program operations is reused for identifying cells requiring repair. The row enable indicator and address matching logic serve dual purposes - normal operation and repair operation - thereby improving reliability without proportionally increasing device complexity.
Solution Approach 2:
The system uses its own operational parameters (row address, column address, block address) during program operations to automatically identify and locate cells requiring repair. The control logic directs repair operations using existing addressing mechanisms, allowing the system to service itself without requiring entirely separate repair control hardware.
Data Source
AI summary
Method of operating memory including storing and/or using an identifier indicating repair of a memory cell.