Flash Memory Cell String With Folded Gate
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Solution Overview
Problem
Existing NAND flash memory devices face challenges in size reduction and performance due to short-channel effects and increased threshold voltage distribution as gate lengths decrease below 40 nm, limiting the degree of integration and memory capacity.
Innovation Solution
A flash memory cell string is designed without source/drain regions or with non-overlapping source/drain regions, utilizing a buried insulating layer to form an inversion layer through fringing electric fields, enhancing current flow and reducing short-channel effects, and incorporating a transmissive insulating layer and charge storage node to improve device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is reduced to increase the degree of integration, then memory capacity increases, but short-channel effects worsen and threshold voltage distribution increases
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional folded gate structure. The gate electrode is folded back on itself, creating multiple gate segments that wrap around the channel region. This dimensional change allows the gate to maintain effective control over the channel even as the overall device footprint is reduced, thereby suppressing short-channel effects while enabling higher integration.
Solution Approach 2:
The folded gate structure nests multiple gate segments within a compact space. The gate electrode folds back and overlays portions of itself, creating a nested configuration where inner gate segments are surrounded by outer segments. This nesting allows the gate to exert enhanced control over the channel region without increasing the device area, thus maintaining reliability while improving integration density.
2Volume of moving object
If the gate length is reduced below 40 nm, then device size decreases, but threshold voltage distribution increases making multi-level cell implementation difficult
Solution Approach 1:
By folding the gate electrode into a three-dimensional structure, the patent achieves effective gate control with a smaller projected device area. The folded configuration allows the gate to wrap around the channel, providing uniform electric field distribution and consistent threshold voltage across the channel region, even when the overall device dimensions are reduced below 40 nm.
Solution Approach 2:
The folded gate structure introduces asymmetry in the gate configuration, with gate segments positioned at different locations around the channel. This asymmetric arrangement allows for optimized electric field distribution and better control over threshold voltage uniformity, compensating for the challenges posed by reduced device dimensions.
3Reliability
If source/drain regions are formed to overlap the control electrode, then device characteristics improve, but short-channel effect increases at channel length of 40 nm or less
Solution Approach 1:
The folded gate structure elevates the gate control into three dimensions, allowing the gate to extend over and around the channel region without requiring source/drain overlap. The vertical and lateral extension of the folded gate segments provides sufficient electrostatic control to suppress short-channel effects while maintaining excellent device characteristics.
Solution Approach 2:
The gate electrode is segmented into multiple folded sections, each contributing to channel control. This segmentation allows the gate to exert control forces from multiple directions and locations, effectively suppressing short-channel effects without relying on source/drain overlap. Each gate segment works cooperatively to maintain uniform threshold voltage and reduce harmful short-channel phenomena.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses short-channel effects, increases read current, and improves size reduction characteristics, enabling higher integration and performance without the need for source/drain regions, thus enhancing the overall performance and capacity of NAND flash memory devices.
Implementation Method 1
utilizing a buried insulating layer to form an inversion layer through fringing electric fields
Data Source
AI summary
The present invention relates to a flash memory cell string. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, and a transmissive insulating layer, a charge storage node, a control insulating layer and a control electrode sequentially formed on the semiconductor substrate. In the flash memory cell string, a buried insulating layer is provided on the semiconductor substrate between the cell device and an adjacent cell device, thus enabling an inversion layer, which performs the functions of source/drain, to be easily formed.According to the present invention, the reduction characteristics and performance of the cell devices of NAND flash memory are improved, and the inversion layer of a channel is induced through fringing electric fields from the control electrode and the charge storage node if necessary.