Flash Memory Cell Structure with Thinned Select Gate
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Solution Overview
Problem
Existing flash memory fabrication methods require multiple lithography operations and struggle with void-free gap fill due to high recess aspect ratios, affecting memory cell performance and stability.
Innovation Solution
The semiconductor structure incorporates a novel processing flow that includes thinning select and erase gates, shared conductive contact plugs, and a dielectric layer to reduce the recess aspect ratio, enabling efficient void-free gap fill and improved memory cell performance by simplifying lithography and enhancing structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithography operations are used in existing flash memory fabrication, then memory cell structure precision can be maintained, but manufacturing complexity and production time increase
Solution Approach 1:
The patent combines multiple lithography operations into a single lithography step by designing a unified patterning process that forms both the select gate and control gate structures simultaneously. This merging approach maintains the required structural precision while reducing manufacturing complexity and production time.
Solution Approach 2:
The invention creates a multi-functional lithography mask that serves multiple purposes: defining select gate patterns, control gate patterns, and alignment features all in one operation. This universal mask design eliminates the need for separate lithography steps while maintaining precision across all structures.
2Volume of moving object
If high recess aspect ratios are used in memory cell structures, then vertical integration density increases, but void-free gap fill becomes difficult affecting performance
Solution Approach 1:
The patent applies local quality by modifying the gap fill process specifically in the recess regions with tailored material deposition and etch conditions. This localized approach ensures complete void-free filling in the critical high aspect ratio regions while maintaining overall structural integrity and performance.
Solution Approach 2:
The invention performs preliminary actions by pre-conditioning the recess surfaces and optimizing the gap fill material properties before the actual deposition. This preliminary preparation enables successful void-free filling even in high aspect ratio structures by reducing surface tension and improving material flow into the recesses.
3Manufacturing precision
If select and erase gates are thinned to reduce recess aspect ratio, then gap fill quality improves, but gate structural strength may be compromised
Solution Approach 1:
The patent employs composite materials by combining multiple gate materials with complementary properties - a thinner structural layer for reduced aspect ratio and improved gap fill, reinforced with a conductive material layer that provides both electrical functionality and structural strengthening. This composite approach maintains gate strength while enabling the thinned configuration.
Solution Approach 2:
The invention changes material parameters by selecting materials with higher strength-to-thickness ratios for the gate structures. By adjusting material composition and properties, the gates can be thinned to reduce the recess aspect ratio while maintaining adequate structural strength through superior material characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of lithography operations, ensures consistent voltage distribution, and improves memory cell performance by minimizing voids in gap fill operations, leading to enhanced stability and efficiency in flash memory fabrication.
Implementation Method 1
A silicidation operation is performed for the source region and the select gate of the memory cell
Data Source
AI summary
The present disclosure presents a method of manufacturing a semiconductor structure, in which a memory cell is formed on a semiconductor substrate, the memory cell including a control gate, a select gate and a source region. A logic device is formed on the semiconductor substrate, where the logic device includes a gate layer and a source/drain region. The select gate is thinned such that the select gate is lower than an upper surface of the control gate. A silicidation operation is performed for the source region and the select gate of the memory cell, and a dielectric layer is deposited over the source region and the drain region of the memory cell, and the drain/source region of the logic device.