Flash Memory Charge Loss Compensation via Preliminary Programming Pulses
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Solution Overview
Problem
Flash memory devices experience quick charge loss after programming, leading to reduced data retention and errors in multiple level cell devices due to immediate shifts in threshold voltage, necessitating enlarged voltage distributions that can overlap and reduce programmable states.
Innovation Solution
Implementing additional programming pulses between the last successful programming pulse and the verify operation, with a slower programming rate achieved by biasing the bit line at a voltage between the inhibit supply voltage and ground potential, to compensate for quick charge loss and maintain target threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If programming pulses are applied to increase the floating gate charge level, then the cell's threshold voltage increases to the desired programmed level, but quick charge loss causes the threshold voltage to shift lower immediately after programming
Solution Approach 1:
The patent applies preliminary action by issuing at least one additional programming pulse to the target cell after the verify operation indicates successful programming. This additional pulse compensates for the anticipated quick charge loss that will occur immediately after programming, ensuring the threshold voltage remains at or above the desired level. The bit line is biased at a voltage between the inhibit supply voltage and ground potential during this additional programming to achieve the compensation effect.
2Reliability
If the threshold voltage distribution is enlarged to accommodate quick charge loss, then all possible threshold voltages can be accommodated, but the number of programmable states is reduced and distributions may overlap
Solution Approach 1:
By applying an additional programming pulse after the verify operation, the patent proactively compensates for quick charge loss before it degrades the threshold voltage distribution. This prevents the need to enlarge the distribution to accommodate charge loss, thereby maintaining tight voltage distributions that support multiple closely-spaced states without overlap.
3Productivity
If verification is performed immediately after programming, then programming time is reduced, but quick charge loss causes the cell to fail verification after passing initially
Solution Approach 1:
The patent maintains continuity of useful action by immediately issuing an additional programming pulse to the target cell after the verify operation indicates successful programming, before the cell is inhibited. This continuous programming action compensates for quick charge loss without interrupting the programming flow or requiring a separate verification cycle, thus maintaining high productivity while ensuring verification accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces quick charge loss without impacting memory performance, ensuring accurate data retention and maintaining the number of programmable states in flash memory devices.
Implementation Method 1
The programming pulse increases a charge level, thereby increasing the cell's threshold voltage Vt, on a floating gate of the memory cell
Implementation Method 2
Intrinsic charge loss is an immediate leakage of electrons from the floating gate, closest to the tunnel oxide, after a programming pulse
Implementation Method 3
Quick charge loss is the result of electrons trapped in the tunnel oxide layer after the programming pulse moving back into the channel region
Data Source
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AI summary
A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.