Flash Memory Charge Tiering for Higher-Density Reliable Storage

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Solution Overview

Problem

Conventional flash memory technologies using multiple data levels per cell are prone to errors during read and write operations and are limited to storing data levels corresponding to even powers of two, which restricts their capacity and reliability.

Innovation Solution

The system employs a flash memory configuration with programmable target charge levels that can define a non-integer power of two data values, using error correction and compensation methods to enhance data storage and retrieval accuracy, including a controller that accesses and adjusts memory cells to establish corrected charge levels based on performance characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple data levels are stored within a single memory cell, then data storage capacity is increased, but error proneness during read and write operations increases

Engineering Contradiction:
Improvedata storage capacityVSAvoiderror rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent divides the charge storage capacity into multiple discrete charge tiers, each representing a specific data level. This segmentation allows the memory cell to store multiple data levels (2, 3, 4, or more levels) by assigning target charge levels to each tier, thereby increasing storage capacity while maintaining reliable distinction between levels through programmed charge thresholds.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If conventional flash memory uses multiple data levels per cell, then storage capacity increases, but the system is limited to storing data levels corresponding to even powers of two

Engineering Contradiction:
Improvestorage capacityVSAvoiddata level flexibility
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent implements a dynamic charge tier structure where the number of charge levels can be programmably adjusted between 2, 3, 4, or more levels based on operational requirements. This dynamic configuration allows the memory system to adapt between different storage capacities and data level representations, breaking the conventional limitation to even powers of two while optimizing for specific application needs.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If target charge levels are programmably movable, then adaptability of data storage increases, but complexity of the processing arrangement increases

Engineering Contradiction:
Improvecharge level configurabilityVSAvoidprocessing arrangement complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent employs programmable parameters that define target charge levels for each charge tier. These parameters can be adjusted to move charge tiers up or down within the charge storage capacity, allowing flexible configuration of data levels. The processing arrangement uses these programmable parameters to control charge pumping operations, enabling adaptability without requiring complex hardware reconfiguration.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20120278684A1Solid state storage element and method
Publication Date: 2012.11.01 BENHOV GMBH LLC
  • US20120278684A1 patent drawing
  • US20120278684A1 patent drawing
  • US20120278684A1 patent drawing

AI summary

A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity.