Flash Memory Clock Control Circuit for Power Saving
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Solution Overview
Problem
The increasing operating frequency of flash memory devices leads to higher electrical power consumption, limiting the capacity of memory stores and necessitating a reduction in power usage.
Innovation Solution
A non-volatile semiconductor memory device with a clock control circuit that switches between tracking and decoupling from the input clock signal, allowing for reduced power consumption during erase operations by altering its operational state in response to commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating frequency of flash memory devices is increased to achieve higher speed operations, then the operation speed is improved, but the electrical power consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock signal generation adaptive rather than static. The clock control circuit dynamically adjusts the clock signal characteristics based on the current operation type (read/write versus erase), allowing the system to optimize power consumption while maintaining high-speed performance when needed. This resolves the contradiction by enabling high speed operations when necessary while reducing power consumption during less demanding operations.
Solution Approach 2:
The patent changes the clock signal parameters (frequency, duty cycle, or presence) based on the operation being performed. During erase operations, the clock signal is modified or stopped, while during read/write operations, the clock signal maintains its high-speed characteristics. This parameter adjustment allows the system to achieve high speed when needed while consuming less power during erase operations, directly resolving the technical contradiction.
2Measurement precision
If the reference clock signal continuously tracks the input clock signal to maintain synchronization, then the timing accuracy is improved, but the power consumption of the module increases
Solution Approach 1:
The patent implements periodic action by having the clock control circuit intermittently update or re-synchronize the reference clock signal with the input clock signal rather than maintaining continuous tracking. The circuit determines when synchronization updates are necessary based on operation type, stopping the continuous tracking during erase operations. This periodic synchronization maintains timing accuracy when needed while significantly reducing power consumption during periods when high precision timing is less critical.
Data Source
AI summary
A non-volatile semiconductor memory device, which comprises (i) an interface having an input for receiving an input clock and a set of data lines for receiving commands issued by a controller including an erase command; (ii) a module having circuit components in a feedback loop configuration and being driven by a reference clock; (iii) a clock control circuit capable of controllably switching between a first state in which the reference clock tracks the input clock and a second state in which the reference clock is decoupled from the input clock; and (iv) a command processing unit configured to recognize the commands and to cause the clock control circuit to switch from the first state to the second state in response to recognizing the erase command. The module consumes less power when the reference clock is decoupled from the input clock than when the reference clock tracks the input clock.