Flash Memory CMOS Logic Integration via Recessed Substrate Segmentation
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Solution Overview
Problem
The integration of Flash memory and CMOS logic circuitry on the same semiconductor die is challenging due to the need to manage different vertical topographies and the disparities in aspect ratios between Flash array features and logic circuitry structures, leading to potential errors and reduced die yield.
Innovation Solution
The solution involves fabricating Flash memory cells in a recessed area of the substrate, where the Flash memory cell gate stack and wordline transistor are formed, and then forming CMOS logic circuitry in a non-recessed area, optimizing the depth of the recessed area to ensure the gate oxide layer for logic circuitry is substantially coplanar with the top surface of the Flash memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Flash memory and CMOS logic circuitry are integrated on the same semiconductor die, then device functionality and integration density are improved, but manufacturing complexity and processing errors increase due to different vertical topographies and aspect ratios
Solution Approach 1:
The semiconductor die is divided into two distinct regions: a first region containing Flash memory circuitry and a second region containing CMOS logic circuitry. This segmentation allows each region to be optimized independently for its specific function while being fabricated on the same die, resolving the contradiction between integration benefits and processing complexity.
Solution Approach 2:
Different gate oxide layer configurations are applied to different regions: the first region (Flash memory) uses a gate oxide layer without nitridation, while the second region (CMOS logic) uses a gate oxide layer with nitridation. This local differentiation allows each region to have the optimal structure for its function, reducing processing errors while maintaining integration.
2Reliability
If different gate oxide layer treatments are used for Flash memory and CMOS logic, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The die is segmented into regions with different gate oxide treatments, allowing Flash memory to use non-nitridated oxide for high-speed operation while CMOS logic uses nitridated oxide for stability, achieving different performance characteristics without compromising manufacturing precision through region-specific optimization.
Solution Approach 2:
Nitridation is applied selectively only to the gate oxide layer in the CMOS logic region, while the Flash memory region maintains non-nitridated oxide. This localized treatment achieves the desired performance differentiation while simplifying manufacturing by avoiding the need to reprocess the entire die multiple times.
3Productivity
If Flash memory cells are formed in a recessed area, then aspect ratio disparities are reduced and die yield is improved, but additional fabrication steps are required
Solution Approach 1:
The Flash memory region is formed in a recessed area (vertical dimension) relative to the CMOS logic region. This dimensional change equalizes the effective aspect ratios of transistors in both regions, improving die yield by reducing processing errors during subsequent fabrication steps, while the recessed structure is integrated into the overall fabrication process.
Data Source
AI summary
An integrated circuit (IC) including Flash memory and CMOS logic circuitry and a method of fabrication thereof is disclosed. The IC comprises a substrate including a recessed area of a first region, a Flash memory cell gate stack formed in the recessed area, a wordline (WL) transistor formed in the recessed area and coupled with the Flash memory cell gate stack, the WL transistor including a WL gate formed over a first gate oxide layer exclusive of nitridation, and a transistor formed in a second area of the substrate separate from the recessed area, the transistor forming at least a portion of logic circuitry of the IC and including a second gate oxide layer having nitridation.