Flash Memory Module Coherence Controller Latency
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Solution Overview
Problem
Existing memory solutions fail to meet the high performance requirements of advanced processors, particularly in terms of bandwidth and efficiency, due to limitations in access latency, cost, and write performance across different memory types.
Innovation Solution
A system comprising a flash memory module with a memory buffer and a coherence directory controller, which processes read and write requests by mapping addresses to cache lines, sending coherency messages, and managing cache coherence to optimize data access and storage across multiple processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If flash memory is used to provide non-volatile storage with lower cost and smaller cell size, then manufacturing cost is reduced and storage density is improved, but access latency increases and write performance deteriorates
Solution Approach 1:
The memory system is segmented into multiple components: flash memory for non-volatile storage, DRAM buffer for fast temporary storage, and HBM for high-bandwidth caching. This segmentation allows each component to operate in its optimal performance range while collectively addressing both cost and latency requirements.
Solution Approach 2:
A coherence directory controller acts as an intermediary between the processor and the hybrid memory system, managing address mapping and data coherence. This intermediary optimizes access patterns by predicting future accesses and pre-fetching data, thereby reducing effective access latency while maintaining flash memory's cost advantages.
2Speed
If DRAM is used to provide fast access performance with good read and write speed, then access speed is improved, but manufacturing cost increases and periodic refresh is required
Solution Approach 1:
DRAM is deployed locally in a buffer within the memory module to cache frequently accessed data, providing fast access speed where needed. Flash memory is used for bulk non-volatile storage where cost is more critical. This local quality approach ensures high-speed access for hot data while using cost-effective flash for cold data.
Solution Approach 2:
The system dynamically changes operational parameters by adjusting cache replacement policies and data placement strategies based on access patterns. This allows the system to optimize the balance between DRAM and flash memory usage, minimizing refresh overhead while maintaining fast access performance.
3Productivity
If memory bandwidth is increased to meet processor performance requirements, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent merges flash memory, DRAM buffer, and HBM into a single integrated memory module with unified control logic. This consolidation provides high bandwidth through multiple parallel interfaces while managing complexity through integrated control rather than separate systems.
Solution Approach 2:
The system adds temporal dimension to memory access by implementing predictive pre-fetching and caching strategies. Data is loaded into the DRAM buffer in advance of actual access needs, effectively increasing bandwidth without requiring proportionally higher physical data transfer rates.
Data Source
AI summary
A method for processing a read request identifying an address. The method includes receiving, at a module including a flash memory and a memory buffer, the read request from a requesting processor, mapping, using a coherence directory controller within the module, the address to a cache line in a cache memory associated with a remote processor, and sending a coherency message from the module to the remote processor to change a state of the cache line in the cache memory. The method further includes receiving, at the module, the cache line from the remote processor, sending, using processor bus and in response to the read request, the cache line to the requesting processor, identifying a requested page stored within the flash memory based on the address, storing a copy of the requested page in the memory buffer, and writing the cache line to the copy of the requested page.