Flash Memory Column Redundancy for Defective Cell Repair
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Solution Overview
Problem
Existing flash memory devices face inefficiencies in using redundant columns for defective memory cells, as they often require real-time address comparison and replace entire columns, leading to ineffective use of memory cells and potential data bottlenecks.
Innovation Solution
A column redundancy scheme that maps data from defective addresses to redundant addresses after data loading, eliminating the need for real-time address comparison and allowing per-bit or per-byte level redundancy, thereby optimizing the use of redundant memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If real-time address comparison is performed during data loading to map defective addresses to redundant columns, then defective memory cells can be repaired, but data bottlenecks occur and I/O speed is reduced
Solution Approach 1:
The patent applies preliminary action by pre-loading all data into the page buffer before performing any address comparison or redundancy mapping operations. This separates the data loading phase from the defect handling phase, allowing the I/O interface to operate at full speed during data loading without being blocked by real-time address comparison operations. The address comparison and mapping are performed only after the data is already in the buffer, thus eliminating the data bottleneck.
2Reliability
If entire columns are replaced when a single memory cell is defective, then the defective cell is repaired, but redundant memory cells are wasted
Solution Approach 1:
The patent applies segmentation by enabling redundancy mapping at the byte level or even bit level within a column, rather than replacing entire columns. The page buffer can identify and map only the specific defective bytes or bits to corresponding redundant locations, allowing the rest of the column to remain functional. This granular approach maximizes the utilization of redundant memory cells by repairing only the minimum necessary portions.
Solution Approach 2:
The patent applies local quality by allowing different portions of a column to have different functional states - some bytes or bits may be mapped to redundant columns while other portions remain in their original locations. This enables selective repair where only the defective portions are redirected to redundancy, while the healthy portions continue to operate normally, thus avoiding the waste of replacing entire columns.
3Reliability
If address comparison is performed in real-time during data loading, then defective addresses can be identified, but the architecture becomes complex and timing constraints are difficult to meet
Solution Approach 1:
The patent applies preliminary action by performing the address comparison operation after data loading is complete, rather than during the loading process. This allows the use of simpler comparison logic that does not need to operate at I/O speeds, reducing the timing constraints and architectural complexity. The page buffer can perform the comparison at its own pace using less complex circuitry.
4Reliability
If real-time address comparison is performed during data loading, then defective addresses can be identified, but timing constraints become difficult to meet
Solution Approach 1:
The patent applies preliminary action by separating the data loading operation from the address comparison operation. All data is loaded into the page buffer first without interruption, and only after the loading is complete does the system perform the address comparison to identify defective addresses. This eliminates the timing conflict between I/O speed requirements and comparison operation requirements, as the comparison occurs after the time-critical loading phase is complete.
Data Source
AI summary
Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion of the second data is written to a column of the memory array associated with the address of the memory determined to indicate a defective memory cell for the first data. Apparatus include memory control circuitry configured to select a portion of data for mapping to a different address in response to an address indicating a defective memory cell, and further configured to select a different portion of data for a particular row than for a different row, wherein the particular row and the different row are associated with the same columns of the memory array.