Flash Memory Column Scan Pass Fail Check Circuit
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Solution Overview
Problem
Flash memory devices face inefficiencies in programming due to repeated program loops required for 'slow cells' or 'fail bit cells,' which increase program time and stress on normally programmed cells, leading to decreased reliability and performance.
Innovation Solution
A flash memory device with a pass/fail check circuit and control logic circuit that verifies data bits during a column scan operation, detects fail data bits, and controls the generation of column addresses based on a reference value to optimize program loops, reducing unnecessary iterations and stress on cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repeated program loops are performed to program slow cells or fail bit cells, then all memory cells including slow cells can be programmed, but program time increases and stress on normally programmed cells increases leading to decreased reliability
Solution Approach 1:
The patent segments the verification process by introducing a pass/fail check circuit that divides memory cells into verified and unverified groups. The column scan operation segments the programming verification into discrete addressable units, allowing selective re-programming only of fail bit cells rather than repeating the entire program loop for all cells.
Solution Approach 2:
The pass/fail check circuit performs preliminary verification of programmed data bits before completing the programming operation. By detecting fail data bits in advance through the column scan operation and comparing against reference values, the system can identify which cells require additional programming cycles, preventing unnecessary repeated programming of already successfully programmed cells.
2Manufacturing precision
If repeated program loops are performed for slow cells, then programming completeness is achieved, but program performance decreases
Solution Approach 1:
The patent implements a feedback mechanism where the pass/fail check circuit continuously monitors programmed data bits and provides feedback to the control logic. The column scan operation reads back programmed values and compares them with reference values, generating feedback signals that indicate whether programming was successful. This feedback allows the system to adjust programming operations dynamically, ensuring completeness while optimizing performance by avoiding unnecessary re-programming cycles.
Solution Approach 2:
The verification operation performs preliminary checking of programmed data before finalizing the programming process. By using the pass/fail check circuit to verify data bits and detect fail bits in advance, the system can determine programming completeness without requiring multiple full program loops, thus maintaining high program performance while achieving complete programming coverage.
3Measurement precision
If column scan operation is performed to verify all data bits, then programming accuracy is improved, but operation complexity increases
Solution Approach 1:
The pass/fail check circuit serves multiple functions: it verifies programmed data bits, detects fail data bits, generates pass/fail signals, and works in conjunction with the column scan operation to provide comprehensive verification. This multi-functional approach improves programming accuracy without requiring separate dedicated circuits for each verification task, thereby limiting the increase in device complexity.
Solution Approach 2:
The column scan operation acts as an intermediary between the programming operation and the pass/fail check circuit. It provides a systematic method for addressing and verifying data bits, bridging the gap between raw programming and final verification. This intermediary structure organizes the verification process in a manageable way, improving accuracy while keeping operational complexity controlled through structured address scanning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces program time and stress on normally programmed cells by minimizing repeated program loops for fail bit cells, thereby enhancing program performance and reliability.
Implementation Method 1
The memory cell of the NAND flash memory 10 is erased and programmed through a Fowler-Nordheim tunneling current.
Data Source
AI summary
A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns. The pass/fail check circuit verifies whether data bits selected by a column address during a column scan operation have program data values. The control logic circuit detects fail data bits from the selected data bits and stores the column address in response to the verification result of the pass/fail check circuit. The control logic circuit also compares a number of the fail data bits with a reference value and controls generation of the column address according to the comparison result.