Non-Volatile Flash Memory Verification Recovery and Column Seeding

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Solution Overview

Problem

Existing non-volatile memory technologies face challenges in efficiently programming and verifying flash cells due to unwanted residue electrons and disturb effects, particularly when programming in reverse order, which affect charge distribution and readability of multi-state values.

Innovation Solution

Implementing reverse order programming with top-to-bottom extended verification recovery and bottom-side seeding of flash memory cells, where residue electrons are pushed down the column and seed charge is injected from the source line, ensuring efficient charge distribution and reduced disturb effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional programming order is used, then programming process is simple, but residue electrons cause charge distribution spread and reduce multi-state storage accuracy

Engineering Contradiction:
Improvecharge distribution uniformityVSAvoidprogramming sequence complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies reverse order programming by programming word lines from top to bottom instead of the conventional bottom to top approach. This inversion allows residue electrons to be naturally pushed down the column during verification recovery, eliminating charge distribution spread without requiring complex additional recovery sequences.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent performs extended verification recovery after programming each word line before moving to the next one. This preliminary recovery action ensures that residue electrons are removed from each word line's column before subsequent programming operations, preventing charge distribution spread and improving multi-state storage accuracy.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If extended verification recovery is performed after each programming operation, then charge distribution uniformity is improved, but programming time is increased

Engineering Contradiction:
Improvecharge distribution uniformityVSAvoidprogramming cycle time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

By reversing the programming order to top-to-bottom, the patent enables verification recovery to proceed automatically in the same direction as programming. This eliminates the need for separate recovery sequences and reduces overall programming time while maintaining charge distribution uniformity.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent integrates verification recovery into the programming sequence by performing it continuously after each programming operation without requiring additional time steps. The recovery process overlaps with or immediately follows programming, ensuring charge distribution uniformity is maintained without significant time penalty.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If conventional bottom-to-top programming is used, then column charge recovery is simplified, but disturb effects increase and multi-state value readability decreases

Engineering Contradiction:
Improvemulti-state value readabilityVSAvoidprogramming sequence complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent inverts the programming sequence to top-to-bottom, which causes residue electrons to be pushed down the column during verification recovery. This natural electron flow direction eliminates disturb effects on lower word lines and improves the readability of multi-state values without requiring complex additional sequences.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent performs verification recovery after programming each word line to preemptively remove residue electrons before they can cause disturb effects during subsequent programming operations. This preliminary anti-action prevents charge distribution spread and maintains multi-state value integrity.

Inventive Principle:
Principle #9Preliminary anti-action

4Productivity

If seed charge is injected from top side, then column seeding is simple, but charge distribution spread increases and programming efficiency decreases

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidcharge distribution uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent inverts the seed charge injection direction to from bottom to top, matching the reverse programming order. This allows seed charge to be injected at the source line and naturally distributed upward through the column, improving programming efficiency and reducing charge distribution spread by aligning with the electron flow direction during verification recovery.

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances programming efficiency and reduces charge distribution spread, improving the reliability and accuracy of multi-state storage in non-volatile memory devices.

Implementation Method 1

residue electrons are pushed down the column

Methodology Applied
Scientific EffectElectron flow: Conduction (electrical)

Implementation Method 2

seed charge is injected from the source line

Methodology Applied
Scientific EffectCharge injection: Conduction (electrical)

Data Source

PatentEP3876235B1Non volatile flash memory with improved verification recovery and column seeding
Publication Date: 2025.10.22 INTEL NDTM US LLC
  • EP3876235B1 patent drawingFigure 1A
  • EP3876235B1 patent drawingFigure 1B
  • EP3876235B1 patent drawingFigure 2A

AI summary

An apparatus is described. The apparatus includes a non volatile memory chip. The non volatile memory chip includes an interface to receive access commands, a three dimensional array of non volatile storage cells, and, a controller to orchestrate removal of charge in a column of stacked ones of the non volatile storage cells after a verification process that determined whether or not a particular cell along the column was programmed with a correct charge amount. The removal of the charge pushes the charge out of the column by changing respective word line potentials along a particular direction along the column. Cells that are coupled to the column are programmed in the particular direction. Disturbance of neighboring cells during programming is less along the particular direction than a direction opposite that of the particular direction.