Flash Memory Post-Write Read Using Combined Page Verification
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Solution Overview
Problem
Conventional error correction codes (ECC) in flash memory systems are resource-intensive and designed for worst-case error rates, leading to performance degradation and inefficiency, especially as the memory ages and error rates increase, requiring a more efficient error management approach.
Innovation Solution
The method involves partitioning the memory array into two portions, where high-density storage cells with smaller error margins operate alongside lower-density cells with wider error margins, allowing for adaptive rewriting of data from the high-density portion to the lower-density portion after a post-write read to detect and correct errors, thereby reducing the computational load on ECC and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC is used to handle worst-case error rates, then data integrity is maintained, but computational load and processing time increase significantly
Solution Approach 1:
The patent applies partial action by implementing a two-stage error correction approach: first using a lightweight parity check on selected pages to identify potential errors, and only then applying full ECC correction when needed. This avoids the excessive computational load of conventional ECC while maintaining data integrity through selective correction.
Solution Approach 2:
The patent segments the error correction process into distinct stages: (1) selective reading of pages based on write patterns, (2) parity bit generation and verification, (3) identification of high error rate pages, and (4) targeted ECC correction. This segmentation allows the system to handle errors efficiently without processing all pages through the full ECC pipeline.
2Quantity of substance
If memory density is increased to store more data, then storage capacity improves, but error rate increases due to smaller error margins
Solution Approach 1:
The patent applies local quality by treating different pages with different verification strategies based on their write patterns. Pages that were written during the same program operation are grouped together and subjected to joint parity verification, while other pages use standard verification. This localized approach optimizes error detection efficiency without compromising overall reliability.
Solution Approach 2:
The patent implements feedback mechanisms where parity check results from initial reads inform subsequent read operations. When high error rates are detected in certain pages, the system uses this feedback to prioritize re-reading and correction of those specific pages, dynamically adjusting the error correction strategy based on actual error conditions.
3Productivity
If multiple pages are read and verified using combined parity checks, then error detection efficiency improves, but memory access time increases
Solution Approach 1:
The patent merges multiple page verification operations into a single combined parity check process. By reading pages in groups and computing parity bits across multiple pages simultaneously, the system achieves efficient error detection without the overhead of individual page verifications, reducing total memory access time while maintaining high error detection efficiency.
Data Source
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AI summary
A post-write read operation, using a combined verification of multiple pages of data, is presented. In a simultaneous verification of multiple pages in a block, the controller evaluates a combined function of the multiple pages, instead of evaluating each page separately. In one exemplary embodiment, the combined function is formed by XORing the pages together. Such a combined verification of multiple pages based on the read data can significantly reduce the controller involvement, lowering the required bus and ECC bandwidth for a post-write read and hence allow efficient post-write reads when the number of dies is large.