Flash Memory Command Completion via Transfer Request Register
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Solution Overview
Problem
Current flash memory systems face performance degradation and latency issues due to the use of software locks and outstanding requests variables, which can lead to race conditions, errors, and delayed or lost commands, especially in multi-core processors.
Innovation Solution
The introduction of a transfer request completion register, mapped to the UFS Transfer Protocol (UTP) Transfer Request List (UTRL) slots, allows the host controller to set and clear bits simultaneously with the doorbell register, eliminating the need for software locks and outstanding requests variables, enabling concurrent completion and issuance of transfer requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software locks and outstanding requests variables are used to manage transfer requests, then race conditions and errors are prevented, but latency increases and performance degrades
Solution Approach 1:
The patent replaces the software-based lock mechanism with a hardware-based completion register. The completion register is a hardware component that automatically sets completion bits when transfer requests are finished, eliminating the need for software locks and context switching. This hardware automation reduces latency while maintaining reliability by preventing race conditions through atomic hardware operations rather than software-controlled locking.
2Reliability
If software locks are used to prevent race conditions, then transfer request exclusions are avoided, but performance in multi-core processors degrades
Solution Approach 1:
The completion register provides a hardware-based mechanism that works efficiently in multi-core environments. Each core can independently check completion bits in the completion register without requiring software locks or mutual exclusion mechanisms. This parallel access capability maintains reliability while enabling multiple cores to operate simultaneously, thus preserving productivity in multi-core processors.
Solution Approach 2:
The completion register automatically tracks and reports transfer request completion status without requiring software intervention. Each transfer request's completion status is self-managed in the hardware register, allowing multiple processor cores to independently query completion status without interfering with each other. This self-service approach eliminates the need for software locks that would otherwise serialize access and reduce multi-core performance.
3Ease of operation
If outstanding requests variables are used to track transfer requests, then command completion can be ascertained, but complexity of software management increases
Solution Approach 1:
The patent replaces software-based tracking variables with a hardware completion register that automatically maintains completion status for all transfer requests. The register contains one bit per transfer request slot, providing a direct hardware mapping between requests and their completion status. This eliminates complex software data structures and management logic, simplifying the system while maintaining ease of operation for ascertaining command completion.
Solution Approach 2:
The completion register serves multiple functions simultaneously: it tracks completion status for all transfer requests, provides atomic read access for multiple cores, and automatically updates on completion events. This single hardware structure replaces multiple software variables and management routines, reducing overall system complexity while maintaining comprehensive tracking capability.
Data Source
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AI summary
Ascertaining command completion in flash memories is disclosed. An exemplary aspect includes eliminating the software lock and the outstanding requests variable and replacing them with a transfer request completion register. The transfer request completion register may be mapped to the universal flash storage (UFS) Transfer Protocol (UTP) Transfer Request List (UTRL) slots. The controller of the host - a hardware component - may set the bit in the transfer request completion register on transfer request completion at the same time the doorbell register is cleared. After this bit has been read, the bit in the transfer request completion register is cleared.