Flash Memory Command Queue Redundancy Removal
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Solution Overview
Problem
Flash memory devices, particularly NAND flash devices, experience 'dirty writes' due to the mismatch between the execution order of host data-update commands and the order of corresponding host commands, leading to errors in data update performance.
Innovation Solution
A method involving the use of two queues, a sequential-update command queue (SCQ) and a random-update command queue (RCQ), where redundant logical addresses are identified and removed to ensure that host data-update commands are executed in the correct order, preventing 'dirty writes' by prioritizing the execution of commands with matching logical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If host data-update commands are executed in the order they are issued by the host side, then the execution order matches the command issuance order, but data update performance deteriorates due to dirty writes
Solution Approach 1:
The patent segments host data-update commands into two separate queues: SCQ (sequential-update command queue) for sequential updates and RCQ (random-update command queue) for random updates. This segmentation allows each queue to handle specific types of updates independently, preventing dirty writes while maintaining overall data update performance through targeted optimization of each queue type.
Solution Approach 2:
The patent performs preliminary classification of host data-update commands into sequential and random types before execution. By pre-categorizing commands based on their update patterns and placing them in appropriate queues, the system prepares the execution order in advance, ensuring that sequential updates maintain order consistency while random updates can be optimized separately, thus avoiding dirty writes before they occur.
2Productivity
If the execution order of host data-update commands does not match the order of corresponding host commands, then data update performance improves, but dirty writes occur leading to errors
Solution Approach 1:
The patent applies different execution strategies to different types of data-update commands by creating specialized queues: SCQ for sequential updates that require order preservation and RCQ for random updates that can be executed independently. This local quality approach ensures that each queue type receives appropriate handling - sequential queues maintain strict ordering to prevent dirty writes, while random queues can be optimized for performance without the same ordering constraints.
3Productivity
If redundant logical addresses are not removed from command queues, then all commands are processed, but execution time increases and performance decreases
Solution Approach 1:
The patent implements a mechanism to detect and discard redundant logical addresses within command queues. When a logical address is found to be redundant (i.e., already present in the queue), the duplicate command is discarded rather than executed. This reduces unnecessary command processing and execution time while maintaining data integrity, as the original non-redundant command will handle the update appropriately.
Data Source
AI summary
The invention introduces a method for scheduling and executing host data-update commands. A first queue and a second queue are provided. The first queue includes first host data-update commands each including a first logical address. The second queue includes second host data-update commands each including a second logical address. A third host data-update command including a third logical address is generated and is labeled as a first type of host data-update command according to a host command received from a host side. A redundant first logical address is removed from a matched one of the first host data-update commands in response that the third logical address is the same as any first logical address. A redundant second logical address is removed from a matched one of the second host data-update commands in response that the third logical address is the same as any second logical address.