Flash Memory Command Scheduling for Data Transfer Efficiency
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Solution Overview
Problem
Flash memory devices, particularly NAND flash devices, face inefficiencies in data read and write operations due to their serial access nature, where commands must be executed in sequences of pages or blocks rather than individual bytes or words, leading to suboptimal data transfer and potential errors like 'dirty reads'.
Innovation Solution
A method and apparatus for scheduling read and write commands using a processing unit that prioritizes executing multiple commands from queues until specific conditions are met, such as tolerable waiting times and avoiding 'dirty reads', by configuring timers and managing queues to optimize continuous data operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If commands are executed sequentially in traditional flash memory, then data transfer completeness is maintained, but data transfer efficiency deteriorates due to serial access constraints
Solution Approach 1:
The patent segments command execution into distinct read command phases and write command phases, executing multiple commands of the same type consecutively before switching types. This segmentation allows the controller to optimize each phase independently, improving overall data transfer efficiency while managing the serial access constraints of flash memory through structured command organization.
Solution Approach 2:
The patent implements preliminary actions by checking whether a read command or write command can be executed before actually executing it. The controller determines the executable command type in advance and prepares the appropriate command structure, allowing for more efficient command scheduling and reducing unnecessary delays in the command execution process.
2Reliability
If read commands are executed without considering write operations, then read speed is maintained, but data correctness deteriorates due to dirty reads
Solution Approach 1:
The patent implements feedback mechanisms where the controller continuously monitors the command queue to determine whether read or write commands can be executed. This feedback loop ensures that read commands are only executed when data is actually available, preventing dirty reads while maintaining optimal read speeds by avoiding unnecessary waits.
Solution Approach 2:
The patent makes the command execution dynamic by adjusting the execution strategy based on real-time conditions in the command queue. The controller dynamically determines whether to execute read or write commands first, and how many commands to execute before switching, optimizing both data correctness and speed based on the current operational state.
3Productivity
If multiple commands are executed continuously, then data transfer efficiency is improved, but command queue management complexity increases
Solution Approach 1:
The patent segments command management into separate read command queues and write command queues, allowing independent management of each type of command. This segmentation simplifies queue management complexity by treating read and write operations separately, while still enabling continuous execution of multiple commands within each queue to maintain high productivity.
4Adaptability or versatility
If serial access protocol is used, then flash memory compatibility is maintained, but data transfer speed deteriorates compared to random access
Solution Approach 1:
The patent implements continuous execution of multiple read or write commands within each phase, maximizing the useful action during serial access operations. By continuously executing commands of the same type without unnecessary interruptions, the system maintains flash memory compatibility while improving data transfer speed through efficient use of the serial access protocol.
Data Source
AI summary
A method for scheduling read and write commands, performed by a processing unit, including at least the following steps: the processing unit obtains more than one read commands from a read queue successively and executes the obtained read commands until a first condition is met. After the first condition is met, the processing unit obtains more than one write commands from a write queue successively and executes the obtained write commands until a second condition is met.