Flash Memory Common Source Region Sawtooth Profile Fabrication

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Solution Overview

Problem

Conventional techniques for forming a common source region in flash memory devices face challenges as device sizes decrease, making it difficult to etch a region for the common source without damaging gate structures, especially due to the aspect ratio and width between field effect transistors.

Innovation Solution

A method is developed to form a common source region before the floating gate and control gate structures, involving the formation of active regions, trench etching, application of a bottom layer, patterning, and ion implantation to create a common source region with a sawtooth or U-shaped profile, followed by dielectric material deposition and gate formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional techniques are used to form a common source region by etching after gate structure formation, then the process follows standard fabrication sequences, but the gate structures are damaged due to high aspect ratio and narrow width between field effect transistors

Engineering Contradiction:
Improvegate structure integrityVSAvoidcommon source region etching
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The common source region is formed by etching before the gate structures are deposited. This preliminary action allows the etching process to proceed without the risk of damaging subsequently formed gate structures, as the gates do not yet exist. The sequence is reversed from conventional approaches: first the common source region is created, then the gate structures are formed overlying the active regions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The conventional sequence of operations is inverted: instead of forming gate structures first and then etching the common source region, the patent etches the common source region first and then forms the gate structures. This inversion of the process sequence eliminates the harmful interaction between the etching process and gate structures while achieving the same functional result.

Inventive Principle:
Principle #13The other way round (Inversion)

2Productivity

If device sizes are decreased to increase memory density, then more memory cells can be packed, but the aspect ratio and width between field effect transistors make etching the common source region difficult without damaging gates

Engineering Contradiction:
Improvememory cell densityVSAvoidcommon source region etching precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The common source region etching is performed as a preliminary step before gate formation, allowing precise etching of narrow regions without the constraint of protecting existing gate structures. This enables the process to accommodate smaller device dimensions and higher memory cell density while maintaining etching precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

By inverting the process sequence to etch the common source region before forming gates, the patent enables scaling to smaller device sizes. The etching process can proceed with higher precision for narrow widths without the risk of gate damage, thus supporting increased memory cell density.

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the successful formation of semiconductor structures with a common source region that can be used in flash memory devices, enabling efficient fabrication without damaging gate structures, even at smaller device sizes.

Implementation Method 1

ion implantation to create a common source region

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS10811504B2Semiconductor structure for flash memory cells and method of making same
Publication Date: 2020.10.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10811504B2 patent drawing
  • US10811504B2 patent drawing
  • US10811504B2 patent drawing

AI summary

An exemplary method includes forming a common source region in a substrate, and forming an isolation feature over the common source region. The common source region is disposed between the substrate and the isolation feature. The common source region and the isolation feature span a plurality of active regions of the substrate. A gate, such as an erase gate, may be formed after forming the common source region. In some implementations, the common source region is formed by etching the substrate to form a saw-tooth shaped recess region (or a U-shaped recess region) and performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region (or the U-shaped recess region), such that the common source region has a sawtooth profile (or a U-shaped profile).