Concurrent Flash Memory Bank Testing via Parallel Control Signals
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Solution Overview
Problem
Flash memory testing is inefficient due to slow access times and the need for numerous read operations across various stress conditions, leading to a linear increase in test time as flash size increases, especially in the 65 nm CMOS manufacturing process.
Innovation Solution
A concurrent testing apparatus and method that includes a memory data path module coupled to a test controller, generating a concurrent control signal to configure multiple flash memory banks for simultaneous testing, using comparators to indicate pass or fail states, and reduction logic to combine status outputs, enabling faster and more efficient testing by reducing the number of read operations required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple read operations are performed per search cycle for each stress condition, then reliability screening is improved, but test time increases linearly
Solution Approach 1:
The patent combines multiple flash memory banks into a single test structure where multiple banks are tested simultaneously through shared test controllers and data paths. This merging approach allows parallel execution of read operations across multiple banks, reducing total test time while maintaining comprehensive reliability screening coverage.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing flash memory banks in a spatial array that can be accessed concurrently. Instead of sequential testing along a single time dimension, the system exploits the spatial dimension by distributing test operations across multiple banks that can be tested simultaneously, effectively breaking the linear time-scaling relationship.
2Quantity of substance
If flash memory size increases, then storage capacity is improved, but test time increases linearly
Solution Approach 1:
The patent segments the flash memory system into multiple independently testable banks, each with its own test control capabilities. This segmentation allows the test system to handle larger total memory capacity by distributing test operations across multiple smaller units that can be tested in parallel, preventing test time from scaling linearly with total memory size.
Solution Approach 2:
The patent creates universal test controllers and data path structures that can handle multiple flash memory banks with the same test logic and control mechanisms. This multi-functionality allows the same test infrastructure to scale to larger memory capacities without proportionally increasing test time, as the universal structures can service multiple banks simultaneously.
3Reliability
If comprehensive stress conditions are applied, then reliability characterization is improved, but number of read operations increases
Solution Approach 1:
The patent maintains continuous useful action by keeping multiple flash memory banks in a ready state and continuously applying stress conditions across all banks simultaneously. Instead of sequentially applying stress conditions to different banks, the system maintains continuous testing activity across the entire memory array, improving productivity while maintaining comprehensive reliability characterization.
Data Source
AI summary
An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access.