Flash Memory Contact Structure Etch Selectivity Control
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Solution Overview
Problem
Current self-aligned contact (SAC) processes in semiconductor technology face challenges with etch selectivity, leading to issues such as hardmask and spacer consumption, resulting in short circuits or open circuits in flash memory devices and logic devices, especially as technology nodes shrink.
Innovation Solution
A method involving a substrate structure with a semiconductor substrate, gate structures, and dielectric layers, where a first dielectric layer forms a mask member with a second dielectric layer covering it, followed by surface treatment and selective etching to create recesses and openings that expose the active region, optimizing etch selectivity ratios to prevent damage to gate structures and ensure proper contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the etch selectivity of the etch process to etch the contact hole is increased, then the contact hole etching efficiency is improved, but the hardmask and sidewall spacers are excessively etched, causing gate exposure and short circuit
Solution Approach 1:
The patent segments the contact hole etching process into multiple stages by introducing different mask layers (first mask layer on gate, second mask layer for alignment) with different etch selectivities. This allows the etching to proceed in controlled steps, preventing excessive removal of protective layers while maintaining etching efficiency.
Solution Approach 2:
The patent introduces an intermediary mask layer structure between the etch process and the gate/sidewall spacer. This mask layer acts as a buffer that protects the gate and sidewall spacers from excessive etching while allowing the contact hole to be etched efficiently through optimized etch selectivity ratios.
2Reliability
If the etch selectivity of the etch process to etch the contact hole is decreased, then the hardmask and sidewall spacers are protected, but a portion of interlayer dielectric layer and mask layer remain in the contact hole, causing open circuit
Solution Approach 1:
The patent divides the etching process into sequential steps with different selectivity requirements. The first etching step uses optimized selectivity to remove dielectric material while the mask layer remains intact, and subsequent steps complete the contact hole formation without leaving residues, ensuring both protection and cleanliness.
Solution Approach 2:
The patent changes the etch selectivity parameters between different etching steps. By adjusting plasma chemistry, power, and other process parameters, the etch selectivity is optimized for each step to achieve complete removal of dielectric material while preventing residue formation in the contact hole.
3Length of moving object
If the technology node size is reduced, then the device scaling is achieved, but the SAC process becomes more sensitive to etch selectivity changes, worsening the short circuit and open circuit risks
Solution Approach 1:
The patent applies segmentation of the mask and etching process to provide finer control at smaller dimensions. The multi-layer mask structure and staged etching process allow precise control of contact hole formation even as feature sizes shrink, maintaining reliability despite increased process sensitivity.
Solution Approach 2:
The patent adjusts etch process parameters (selectivity ratios, etch rates, plasma conditions) to compensate for the increased sensitivity at smaller technology nodes. By optimizing these parameters, the process maintains robustness and reliability even as device dimensions are reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of short circuits and open circuits, improves the device profile, and enhances the reliability and yield of semiconductor devices by maintaining the integrity of gate structures and contact formation.
Implementation Method 1
an SAC etching of the contact hole is performed using a patterned mask layer 117
Implementation Method 2
performing a surface treatment on the second dielectric layer so that an upper surface of the second dielectric layer is flush with an upper surface of the mask member
Data Source
AI summary
A semiconductor device includes a substrate structure comprising an active region, a first interlayer dielectric layer on the active region, and a first opening in the first interlayer dielectric layer and extending to the active region, at least one gate structure in the first opening and comprising spacers on sidewalls of the first opening, a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and a hardmask on the metal gate and having a first recess in a middle portion of its upper surface, the gate dielectric layer, the metal gate, and the hardmask being between the spacers, a second interlayer dielectric layer on the first dielectric layer and on at least a portion of the hardmask, and a second opening adjacent to the at least one gate structure in the first opening and exposing the spacers and a surface of the active region.