Flash Memory Access Contention via Multi-Channel Segmentation
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Solution Overview
Problem
Flash-based memory systems face significant access contention due to erase and write delays, which can exceed acceptable latency bounds, especially in high-load scenarios, and traditional DRAM technologies do not have these restrictions, making it crucial to provide flash-based memory technologies with similar access characteristics.
Innovation Solution
The implementation of a flash architecture that decouples read, write, and erase operations by grouping flash chips into chip stripes and using a per-channel free-block queue with a write page allocator and garbage-collection algorithm, ensuring that read and write operations are not penalized by preceding erase operations, and providing efficient garbage collection and wear-leveling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory uses blocking erase operations, then erase operations can be performed, but read and write operations are blocked during erase, causing significant access delays
Solution Approach 1:
The flash memory system is divided into multiple independent channels, each capable of handling read, write, and erase operations separately. This segmentation allows parallel execution of operations across different channels, so that a read or write operation on one channel is not blocked by an erase operation on another channel.
Solution Approach 2:
A controller acts as an intermediary between the host and flash memory chips, managing multiple channels and coordinating operations. The controller allocates channels for different operations and handles the complexity of parallel operation management, allowing the system to achieve non-blocking behavior while maintaining reliable erase operations.
2Loss of time
If flash memory performs out-of-place writes to hide block erase latency, then erase latency can be hidden, but a Flash Translation Layer is required to maintain mapping between logical and physical addresses
Solution Approach 1:
The FTL functionality is extracted from the flash memory system and implemented in the controller, which manages multiple channels. This allows the flash memory chips themselves to be simpler while the controller handles the complexity of address mapping and garbage collection, reducing the burden on individual flash chips.
Solution Approach 2:
Each channel in the multi-channel system can perform read, write, and erase operations, providing multi-functionality at the channel level. This universal capability across channels reduces the need for specialized FTL logic in each flash chip, as the controller can dynamically allocate channels for different operations.
3Loss of energy
If flash memory is used to replace battery-backed DRAM (NVRAM), then cost can be reduced, but access delay homogeneity is compromised due to flash's blocking erase characteristics
Solution Approach 1:
The system uses multiple independent channels to segment the flash memory access paths. This allows the system to provide homogeneous access delays by ensuring that read and write operations are never blocked by erase operations on other channels, achieving DRAM-like access characteristics without requiring battery-backed memory.
Solution Approach 2:
The system changes the operational parameters by using parallel multi-channel architecture instead of single-channel flash memory. This parameter change transforms the access delay characteristics from heterogeneous (with blocking erases) to homogeneous (with parallel non-blocking operations), enabling flash memory to replace battery-backed DRAM while maintaining consistent access performance.
Data Source
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AI summary
Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.