Flash Memory Control Circuit Interleaved Data Transfer

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional flash memory storage devices face inefficiencies in data writing speed due to the need for large buffer memories and prolonged wait times when multiple flash memories are busy, especially with multi-level cell NAND flash memories, which increases the complexity and capacity requirements of buffer memory systems.

Innovation Solution

A flash memory control circuit and storage system that groups memory cell arrays into data transfer units (DTUSs) and interleaves data transfer across multiple flash memory units, optimizing data transfer by categorizing pages based on write speed and managing them in a way that reduces the reliance on buffer memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is written into multiple flash memories in an interleaving manner to increase write speed, then the writing speed is improved, but the buffer memory capacity requirement increases

Engineering Contradiction:

Improvewrite speedVSAvoidbuffer memory capacity

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments the flash memory system into multiple independent flash memory units (first flash memory unit, second flash memory unit, etc.), each capable of independent data reception and programming. By dividing the data writing task across multiple segmented units with different programming speeds, the system can interleave data transfers without requiring a proportionally larger buffer, as each unit processes data at its own optimized pace

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The control circuit performs preliminary classification of data into different types (first type data for faster programming, second type data for slower programming) before transferring to flash memory units. This preliminary action allows the system to pre-assign data to appropriate flash memory units based on their capabilities, reducing the need for large buffers to hold data during waiting periods

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the control circuit waits for flash memory programming completion before transferring next data, then data integrity is maintained, but the write speed decreases

Engineering Contradiction:

Improvedata integrityVSAvoidwrite speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The control circuit maintains continuous useful action by transferring different types of data to different flash memory units simultaneously rather than sequentially waiting. While one flash memory unit is programming first type data, the control circuit continues transferring second type data to another flash memory unit, ensuring the data transfer pipeline remains full and productive without compromising integrity through the interleaved approach

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The system dynamically adapts the data transfer strategy based on the programming status of different flash memory units. The control circuit monitors which units are busy and which are available, dynamically assigning data types to appropriate units. This dynamic approach allows continuous operation while maintaining data integrity through proper timing and assignment

Inventive Principle:

Principle #15Dynamics

3Stability of the object's composition

If buffer memory capacity is increased to handle multiple flash memories, then data transfer stability is improved, but the device complexity increases

Engineering Contradiction:

Improvedata transfer stabilityVSAvoidbuffer memory system complexity

Core Design Contradiction:

Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent applies local quality by assigning different data types to different flash memory units based on their specific programming characteristics. First type data is assigned to units capable of faster programming, while second type data is assigned to units with slower programming speeds. This localized optimization allows the system to achieve stable data transfer with minimal buffer requirements, as each unit operates in its optimal performance zone without requiring excessive buffering

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS8606988B2Flash memory control circuit for interleavingly transmitting data into flash memories, flash memory storage system thereof, and data transfer method thereof

Publication Date: 2013.12.10 PHISON ELECTRONICS

AI summary

A flash memory control circuit including a microprocessor unit, a first interface unit, a second interface unit, a buffer memory, a memory management unit, and a data read/write unit is provided. The memory management unit manages a plurality of flash memory units, wherein each of the flash memory units has a plurality of flash memories, each of the flash memories has a plurality of memory cell arrays, and each of the memory cell arrays at least has an upper page and a lower page. The memory management unit groups the memory cell arrays of the corresponding flash memories into a plurality of data transfer unit sets (DTUSs). The data read/write unit interleavingly transfers data to the flash memory units in units of the DTUSs. Thereby, the flash memory control circuit can transfer the data stably and the usage of the buffer memory can be reduced.